Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/68048
標題: Nanoscaled interfacial oxide layers of bonded n- and p-type GaAs wafers
作者: Ouyang, H.
Wu, Y.C.S.
Cheng, J.H.
Lu, C.L.
Chiou, S.H.
Ouyang, W.
關鍵字: temperature;semiconductors;fabrication;resistance;conduction;diffusion;stability;hydrogen;silicon;oxygen
Project: Applied Physics Letters
期刊/報告no:: Applied Physics Letters, Volume 88, Issue 17.
摘要: 
This work examined in detail the electrical characteristics and microstructures of in- and antiphase bonded interfaces for both n- and p-type GaAs wafers treated at 500 and 600 degrees C, respectively. The n-GaAs wafers did not bond directly to itself but instead via an amorphous oxide layer at 500 degrees C. These temperatures are lower than most other works. The nonlinear behavior of the current versus the voltage is related to the potential barrier formed at the continuous oxide interface. Both experimental observation and first-principles calculations confirm the existence of this barrier. The higher interface energy for the antiphase bonding tends to stabilize the interfacial oxide layer. The evolution of interfacial layers occurred much faster for the p-type wafers than for n-type wafers. Electrical performance was found to be closely related to the variation of nanosized interface morphology. (c) 2006 American Institute of Physics.
URI: http://hdl.handle.net/11455/68048
ISSN: 0003-6951
DOI: 10.1063/1.2198511
Appears in Collections:期刊論文

Show full item record
 

Google ScholarTM

Check

Altmetric

Altmetric


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.