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|標題:||High mechanical and electrical reliability of bottom-gate microcrystalline silicon thin film transistors on polyimide substrate||作者:||Huang, J.J.
|關鍵字:||Microcrystalline silicon;Thin film transistor;Transparent polyimide;stability;pecvd;glass||Project:||Current Applied Physics||期刊/報告no：:||Current Applied Physics, Volume 11, Issue 1, Page(s) S266-S270.||摘要:||
Bottom-gate microcrystalline silicon thin film transistors (mu c-Si:H TFTs) were fabricated by conventional 13.56 MHz RF plasma-enhanced chemical vapor deposition at 200 degrees C. In the high pressure depletion regime, the deposition rate of the mu c-Si: H film is 24 nm/min and the amorphous incubation layer near the mu c-Si:H/silicon nitride interface is unobvious. The crystalline fraction of mu c-Si:H film with the thickness of 50 nm is 71%. From nano beam electron diffraction, the mu c-Si: H film has a better crystalline order within a short-range lattice structure. The lattice parameter was measured to be 3.1 angstrom, which reflecting the lattice plane has a (111) direction. Finally, the mu c-Si: H film was used as the active layer in TFTs structure. The field effect mobility, subthreshold swing and the threshold voltage are 0.95 cm(2)/V, 0.85 V/dec. and 2.05 V, respectively. The output characteristic also shows no evidence of current crowing at low drain-source voltage (V(ds)), implying good contact properties achieved with the n(+) a-Si: H source-drain ohmic contact layer. After 70 h 1 mu A constant current stress, the threshold voltage shifts are 4.44 V and 0.42 V for the a-Si: H TFT and mu c-Si: H TFT, respectively. The mu c-Si: H thin film transistors show a better electrical stability than the amorphous silicon thin film transistors because of the lower defect density in the mc-Si: H film. (C) 2010 Elsevier B. V. All rights reserved.
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