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標題: Compact layout of DT-MOS transistor with source-follower subcircuit in 90-nm CMOS technology
作者: Hsu, H.M.
Lee, T.H.
關鍵字: compact layout;Dynamic Threshold-voltage MOS (DT-MOS) transistor;embedded device;source follower;substrate resistance
Project: Ieee Electron Device Letters
期刊/報告no:: Ieee Electron Device Letters, Volume 29, Issue 4, Page(s) 392-395.
This letter proposes a compact layout of the Dynamic Threshold-voltage MOS (DT-MOS) transistor using foundry 90-nm CMOS technology. Adopting the subcircuit of source follower, the proposed DT-MOS transistor could be operated at voltage as low as 0.7 V. Measurement results demonstrate the 80 % improvement of current drive capability and the 60% improvement of transconductance compared to traditional devices. This letter demonstrates an excellent device with compact layout for low-voltage operation by using nanometer CMOS technology.
ISSN: 0741-3106
DOI: 10.1109/led.2008.918255
Appears in Collections:期刊論文

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