Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/6907
標題: 具有單位元錯誤更正的平行CRC-32與其VLSI設計
VLSI Design of A Parallel CRC-32 with Single Error Correction
作者: 李民棟
Li, Min-Dong
關鍵字: CRC;錯誤修正;checksum;correction
出版社: 電機工程學系所
引用: [1] Campobello, G., Patane, G.,Russo, M.” Parallel CRC realization”; Computers, IEEE Transactions on Volume 52,Issue 10, Oct. 2003. Page(s):1312-1319 [2] Shukla, S., Bergmann,N.W.“Single bit error correction implementation in CRC-16 on FPGA”; Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on 2004 Page(s):319 - 322 [3] M.d. Shieh et al., “A System Approach for Parallel CRC omputations, ”IEEE Design and Test of computers,Page(s):445-461, May 2001. [4] Glaise, R.J.; Jacquart, X.;“FAST CRC CALCULATION”,Computer Design: VLSI in Computers and Processors, 1993. ICCD ''93. Proceedings., 1993 IEEE International Conference on 3-6 Oct. 1993 Page(s):602 - 605 [5] Henriksson, T.; Dake Liu; “Implementation of Fast CRC Calculation”, Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific 21-24 Jan. 2003 Page(s):563-564 [6] Henriksson, T.; Dake Liu;” Implementation of fast CRC calculation” Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific 21-24 Jan. 2003 Page(s):563 - 564 [7] Ji, H.M.; Killian, E.;” Fast parallel CRC algorithm and implementation on a configurable processor” Communications, 2002. ICC 2002. IEEE international Conference on Volume 3, 28 April-2 May 2002 Page(s):1813 - 1817 [8] Sprachmann, M.;” Automatic generation of parallel CRC circuits”,Design & Test of Computers, IEEE Volume 18, Issue 3, May-June 2001 Page(s):108 - 114 [9] Derby, J.H.;” High-speed CRC computation using state-space transformations ” Global Telecommunications Conference, 2001. GLOBECOM ''01. IEEE Volume 1, 25-29 Nov. 2001 Page(s):166 - 170 ier [10] Maria, J.; Serrano, N.;” 5/spl times/4 Gbps 0.35 micron CMOS CRC generator designed with standard ce”Electrotechnical Conference, 2002. MELECON 2002. 11th Mediterranean 7-9 May 2002 Page(s):215 - 219
摘要: 
一般而言在通訊傳輸、網路傳輸方面,我們要如何確定在接收端接收的資料是正確的呢?使用的方法蠻多種類的,一般比較常見的方法就是在傳輸的資料後面再加上所謂的Cyclic redundancy check (CRC)來作為檢查碼,以判斷資料是否在傳輸中發生錯誤。Cyclic redundancy check(CRC) 擁有非常強大的偵測與偵錯能力,因此它常用於VLSI偵測和邏輯電路偵錯上,除上述之外像是MAC上也是經常使用到。
雖然CRC擁有非常強大的能力,但是也有一個瓶頸需要去突破,那就是當CRC的錯誤修正能力在硬體上實現時,其speed可能無法到達10Gbps。在目前網路、通訊傳輸速度越來越快的情況之下,若CRC修正無法突破10Gbps,勢必將影響到整個網路、通訊傳輸的速度,這是未來需要突破的地方。
本篇論文修改了[1][2]的硬體架構且將其結合,且提出了一種在FPGA裝置上完成CRC-32硬體實現的有效方法,除可以偵測CRC錯誤與修正單一位元錯誤的能力之外,也可以判斷出是資料發生錯誤還是checksum發生錯誤,以便我們了解錯誤進而去修正錯誤。我們是修改了[1]論文的Parallel circuit使其除了可以處理資料能被多項式(polynomial)整除之外,也能處理資料不能被多項式(polynomial)整除的問題。論文[2]我們擴展了修正的能力使其由原本的16 bit擴展至32 bits以增加處理效能。

How do we want to decide corrects in data at receivers for communications and networks? In general, the cyclic redundancy check (CRC) is popular used for checksum computation. Cyclic redundancy check (CRC) is a powerful class of code, which suits especially for the detection of burst errors in data storage, communication applications, testing of integrated circuits and the detection of logic faults.
CRC acts powerful class of codes for applications, but when the process speed is up to 10 Gbps, the implementations of header error corrections in hardwares can be a bottleneck. At current networks, the speed of communication transmissions is more and more fast. If CRC processes can not speed up to 10 Gbps, it will not achieve the real-time high-speed transmissions and communications. Thus, the high-speed CRC is required to solve the error detection problem in high-speed networks.
In this thesis, we improve hardware architectures in [1] [2] and combine two architectures to implement an effective CRC-32 hardware on FPGA device. The proposed CRC-32 module not only detects CRC error and corrects one bit error but also determines where the one-bit error is in the received information or in the checksum. So we can find out and correct one bit error by additional checksum computations. We improve parallel CRC circuits in [1], which only can deal with input data to be divisible by the polynomial. The proposed CRC-32 can deal with input data, which can not be divisible by the polynomial. We expand one-bit correct ability from 16 bits to 32 bits for increasing error correct performances.
URI: http://hdl.handle.net/11455/6907
其他識別: U0005-2507200622250400
Appears in Collections:電機工程學系所

Show full item record
 

Google ScholarTM

Check


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.