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|標題:||Analytical Design Algorithm of Planar Inductor Layout in CMOS Technology||作者:||Hsu, H.M.
|關鍵字:||Analytical algorithm;minimum resistance;on-chip inductor;variable;width;chip spiral inductors;noise||Project:||Ieee Transactions on Electron Devices||期刊/報告no：:||Ieee Transactions on Electron Devices, Volume 55, Issue 11, Page(s) 3208-3213.||摘要:||
A layout design algorithm for a variable-width inductor is proposed to minimize metal resistance. For a given chip area, the proposed algorithm can rapidly design metal widths of each coil in a planar inductor due to the analytical form. Two on-chip inductors with identical chip areas and inductance are fabricated to verify the proposed method in foundry 90-nm CMOS technology. Measurement results demonstrate that the improvement of metal resistance in the proposed device is approximately 19%. The results of this paper provide an effective algorithm to design a high-Q inductor for RFIC applications.
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