Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/69599
標題: Ultra-shallow junction formation using implantation through capping nitride layer on source/drain extension
作者: Hsien, L.J.
Chan, Y.L.
Chao, T.S.
Jiang, Y.L.
Kung, C.Y.
關鍵字: shallow junction;nitride;CMOS
Project: Japanese Journal of Applied Physics Part 1-Regular Papers Short Notes & Review Papers
期刊/報告no:: Japanese Journal of Applied Physics Part 1-Regular Papers Short Notes & Review Papers, Volume 41, Issue 7A, Page(s) 4519-4520.
摘要: 
Method for forming ultra-shallow p(+)/n is demonstrated for 0.15 mum p-type metal-oxide-semiconductor field-effect transistor (pMOSFET). The approach includes a capping ultra-thin nitride on the source/drain extension regions followed by a low energy source/drain (S/D) extension implantation. Ultra shallow p(+)/n junctions can be obtained with depth of 27 nm and sheet resistivity of 1007 Omega/square.
URI: http://hdl.handle.net/11455/69599
ISSN: 0021-4922
DOI: 10.1143/jjap.41.4519
Appears in Collections:期刊論文

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