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A Modified Parallel Multiplier for Low Order Normal Elements
|關鍵字:||finite field;有限場;normal basis;normal basis multiplier;正規基底;正規基底乘法器||出版社:||電機工程學系所||引用:|| S. Lin and D.J. Costello, Error Control Coding: Fundamentals and Applications. Prentice Hall, 1983.  F.J. MacWilliams and N.J.A. Sloane, The Theory of Error Correcting Codes. New York: North-Holland, 1977.  I.S. Reed and X. Chen, Error-Control Coding for Data Networks. Kluwer Academic Publishers, 1999.  W. Stallings, Cryptography and Network Security: Principles and Practices. Prentice Hall, 2003.  C.C. Wang, T.K. Truong, H.M. Shao, L.J. Deutsch, J.K. Omura, and I.S. Reed, "VLSI Architectures for Computing Multiplications and Inverses in ," IEEE Trans. Computers, vol. 34, no. 8, pp. 709- 716, Aug. 1985.  A. Reyhani-Masoleh and M.A. Hasan,"A New Construction of Massey-Omura Parallel Multiplier over ," IEEE Trans. Computers, vol. 51, no. 5, pp. 511-520, May 2002.  R.C. Mullin, I.M. Onyszchuk, S.A. Vanstone, and R.M. Wilson,"Optimal Normal Bases in ," Discrete Applied Math., vol. 22, pp. 149-161, 1988/1989.  M.A. Hasan, M.Z. Wang, and V.K. Bhargava, "A Modified Massey-Omura Parallel Multiplier for a Class of Finite Fields," IEEE Trans. Computers, vol. 42, no. 10, pp. 1278-1280, Oct. 1993.  I.S. Hsu, T.K. Truong, L.J. Deutsch, and I.S. Reed, "A Comparison of VLSI Architectures of Finite Field Multipliers Using Dual, Normal or Standard Bases, " IEEE Trans. Computers, vol. 37, no. 6, pp. 735-739, June 1988.  E.D. Mastrovito, "VLSI Architectures for Computation in Galois Fields, " PhD thesis, Linkoping Univ., Linkoping, Sweden, 1991.  A. Halbutogullari and C.K. Koc, "Mastrovito Multiplier for General Irreducible Polynomials," IEEE Trans.Computers, vol. 49, no. 5, pp. 503-518, May 2000.  S.T.J. Fenn, M. Benaissa, and D. Taylor, " Multiplication and Division Over the Dual Basis," IEEE Trans. Computers, vol. 45, no. 3, pp. 319-327, Mar.1996  H. Wu, M.A. Hasan, and I.F. Blake, "New Low-Complexity Bit-Parallel Finite Field Multipliers Using Weakly Dual Bases," IEEE Trans. Computers, vol. 47, no. 11, pp. 1223-1234, Nov. 1998.  B. Sunar and C.K. Koc, "Mastrovito Multiplier for All Trinomials," IEEE Trans. Computers, vol. 48, no. 5, pp. 522-527, May 1999.  M. Elia, M. Leone, and C. Visentin, "Low Complexity Bit-Parallel Multipliers for with Generator Polynomial ," Electronics Letters, vol. 35, no. 7, pp. 551-552, Apr. 1999.  M.A. Hasan, M.Z. Wang, and V.K. Bhargava, "Modular Construction of Low Complexity Parallel Multipliers for a Class of Finite Fields ," IEEE Trans. Computers, vol. 41, no. 8, pp. 962-971, Aug. 1992.  C.K. Koc and B. Sunar, "Low-Complexity Bit-Parallel Canonical and Normal Basis Multipliers for a Class of Finite Fields," IEEE Trans. Computers, vol. 47, no. 3, pp. 353-356, Mar. 1998.  H. Wu and M.A. Hasan, "Low Complexity Bit-Parallel Multipliers for a Class of Finite Fields," IEEE Trans. Computers, vol. 47, no. 8, pp. 883-887, Aug. 1998.  C. Paar, "A New Architecture for a Parallel Finite Field Multiplier with Low Complexity Based on Composite Fields," IEEE Trans. Computers, vol. 45, no. 7, pp. 856-861, July 1996.  C. Paar, P. Fleishmann, and P. Roelse, "Efficient Multiplier Architectures for Galois Fields ," IEEE Trans. Computers, vol. 47, no. 2, pp. 162-170, Feb. 1998.  J.L. Massey and J.K. Omura, "Computational Method and Apparatus for Finite Field Arithmetic," US Patent Number 4,587,627, May 1986.  B. Sunar and C.K. Koc, "An Efficient Optimal Normal Basis Type II Multiplier," IEEE Trans. Computers, vol. 50, no. 1, pp. 83-88, Jan. 2001  M. Elia and M. Leone, "On the Inherent Space Complexity of Fast Parallel Multipliers for ," IEEE Trans. Computers, vol. 51, no. 3, pp. 346-351, Mar. 2002.||摘要:||
Recently, implementations of normal basis multiplication over the extended binary field GF(2^m) have received considerable attention. For efficient hardware implementation of finite field arithmetic units, the use of a normal basis is advantageous. The Massey-Omura multiplier of GF(2^m) uses a normal basis and its bit parallel version is usually implemented using m identical combinational logic blocks whose inputs are cyclically shifted from one another. In the past, it was shown that, for a class of finite fields defined by irreducible all-one polynomials, the parallel Massey-Omura multiplier had redundancy and a modified architecture of lower circuit complexity was proposed. In this article, it is shown that, not only does this type of multipliers contain redundancy in that special class of finite fields, but it also has redundancy in fields GF(2^m) defined by any irreducible polynomial. By removing the redundancy, we propose a new architecture for the normal basis parallel multiplier, which is applicable to any arbitrary finite field and has significantly lower circuit complexity compared to the original Massey-Omura normal basis parallel multiplier. The proposed multiplier structure is also modular and, hence, suitable for VLSI realization.
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