Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/6989
標題: 應用於HDTV1080p之H.264/AVC立體高級規範立體影像幀間預測演算法研究及其電路架構設計與實現
Algorithm and Architecture Design of HDTV1080p Stereo Video Inter Prediction Processor in H.264/AVC Stereo High Profile
作者: 詹益昇
Chan, Yi-Sheng
關鍵字: stereo video coding;立體影像編碼;disparity estimation;motion estimation;視差估測;移動估測
出版社: 電機工程學系所
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摘要: 
3D影像能夠透過傳送端傳送影像到人們的眼睛裡,提供人們更高品質與深入其境的視覺享受。在3D影像的系統中,立體影像編碼占了很重要的部分,由於立體影像比傳統2D影像多了一倍的資料量,所以立體影像壓縮技術必須解決這類的問題,有效的大量減低原有資料量並且保留立體影像的良好品質。為了上述的目的,在本論文立體影像編碼將分為兩種階段,第一階段為提出適用於H.264/AVC立體影像編碼系統之快速幀間編碼演算法,第二階段為提出適用於H.264/AVC立體影像編碼系統之快速幀間編碼架構。
演算法層面上,本論文提出一快速幀間二階漸進式移動/視差整數點估測演算法來取代原有的全區域區塊比對搜尋演算法,此演算法利用候選區塊取樣技術,並以二階漸進式的方式,進行區塊比對。此快速演算法可保有和全區域區塊演算法相當的品質,並減少相當大的運算量。再來我們提出了一個基於機率模型的提早中斷視差估測演算法,利用演算法中的方程式求出門檻值,利用門檻值的判斷,使得立體編碼系統在進行完移動估測後能夠先行決定是否要繼續執行視差估測,此演算法也能在減少運算量的同時保持良好的立體影像品質。
硬體層面上,本論文整合我們提出的二階漸進式移動/視差整數點估測演算法以及基於機率模型提早中斷視差估測演算法,完成提出的適用於H.264/AVC立體影像編碼系統之快速幀間編碼架構,其架構可利用單一運算單元完成視差估測以及左右眼的移動估測,並利用記憶體預先讀取的技術,可以大幅的減少以往立體影像編碼系統所花費的時間。
晶片實驗結果採用TSMC Arm 0.09mm 1P9M 標準元件製程,頻率可以達到250Mhz 達到HDTV 1080p即時立體影像標準,功率消耗達到171mW。

Three-dimensional (3D) video offers a high-quality and immersive multimedia to human eyes via sender transmission. In 3D video systems, stereo video coding plays an important role because stereo video doubles the amount of data, comparing with the tradition 2D video. Therefore, stereo video coding must solve this problem so it can effectively reduce the original large amount of date, whereas maintain the good quality in stereo video. For this reason, this thesis stereo video coding will be divided into two stages. At the first stage, we propose fast inter coding algorithm applied in H.264/AVC stereo video coding system; and at the second stage, we propose fast inter coding architecture applied in H.264/AVC stereo video coding.
In terms of algorithm, we propose a fast motion/disparity estimation algorithm based on the coarse-to-fine technique. The proposed algorithm is applied to integer motion/disparity estimator of the H.264 stereo encoder. It performs the local full search on pixels around the selected candidates to obtain the 41 MVs or DVs. The proposed algorithm that compared with full search block match algorithm can keep the good quality and save the amount of computation algorithm. Moreover, we propose an early disparity termination algorithm base on model-based scheme. The threshold values are determined by some equations. When motion estimation is finished, we compare the SAD value of some points with threshold values. If SAD value is smaller than threshold value, disparity will be terminated. This algorithm can also increase with the quality and reduce the computation amount.
In the Hardware, combining the proposed coarse-to-fine algorithm and module-based early disparity termination algorithm, we propose fast inter coding architecture applied in H.264/AVC stereo video coding. This architecture also allows us to use the same computation unit to estimate left view motion and right view motion/disparity. We also use memory preload technology to save stereo video coding time.
The implementation result shows that the proposed Stereo inter prediction processor has 130K logic gates with core size 2.8 × 2.8 mm2. Moreover, In the TSMC 0.09mm 1P9M CMOS process, the H.264/AVC Stereo High Profile HDTV1080p applications at 250 MHz.
URI: http://hdl.handle.net/11455/6989
其他識別: U0005-2202201202550000
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