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標題: 低成本高效能的AES加解密處理器設計與FPGA實作
FPGA Implementation and Design of a Low-Cost and High Performance AES Processor
作者: 陸育新
Lu, Yu-Hsin
關鍵字: encryption;加密;decryption;AES;composite field;解密
出版社: 電機工程學系所
引用: [1] 賴溪松,韓亮,張真誠合著,“近代密碼學及其應用", 旗標出版股份 有限公司,2003。 [2] 粘添壽,吳順裕合著,“資訊與網路安全技術",旗標出版股份有限公 司,2004。 [3] 王信中.林志修.吳安宇,“具成本效益的AES加密引擎之設計與實現”, 國立臺灣大學「台大工程」學刊第八十八期,民國九十二年六月。 [4] “Advanced Encryption Standard(AES)”, Federal Information Processing Standards Publication 197, November 26,2001. [5] Vincent Rijmen, “Efficient Implementation of the Rijndael S-box”, Available at [6] Xinmiao Zhang and Keshab K. Parhi, “Implementation Approaches for the Advanced Encryption Standard Algorithm”, Circuits and Systems Magazine, IEEE , Volume: 2 , Issue: 4 , pp. 24-46, 2002. [7] Xinmiao Zhang and Keshab K. Parhi, “High-Speed VLSI Architectures for the AES algorithm”, IEEE Transaction on Very Large Scale Integration (VLSI)Systems, vol. 12, no. 9, pp. 957-967, September 2004. [8] Alireza Hodjat, Ingrid_Verbauwhede, “A 21.54 Gbits/s fully pipelined AES processor on FPGA”, IEEE Symposium on Field -Programmable Custom Computing Machines, April 2004. [9] Alireza Hodjat and Ingrid Verbauwhede, “Speed-area trade-off for 10 to 100 Gbits/s throughput AES processor”, Conference Record of the Thirty- Seventh Asilomar Conference on Signals, Systems and Computers, Nov 9-12, 2003 pp.2147-2150. [10] Alireza Hodjat and Ingrid Verbauwhede, “Minimum Area Cost for a 30 to 70 Gbits/s AES processor”, Proceedings. IEEE Computer society Annual Symposium on VLSI, Feb 19-20, 2004, pp.83-88. [11] K. U. Jarvinen, M. T. Tommiska, and J. O. Skytta, “A fully pipelined me- moryless 17.8 Gbps AES-128 encryptor,” in Proc. Int. Symp. Field-Pro- grammable Gate Arrays (FPGA 2003), Monterey, CA, Feb. 2003,pp. 207–215. [12] C. C. Lu and S. Y. Tseng, “Integration of AES (Advanced Encryption Standard) encrypter and decrypter,” Proceeding, Application-Specific Systems, Architecture and Processor, 2002, pp. 277.285. [13] A. Satoh, S. Morioka, K. Takano, and S. Munetoh, “A compact Rijndael hardware architecture with S-Box optimization,” in Proc. ASIACRYPT 2001, Gold Coast, Australia, Dec. 2000, pp. 239–254. [14] A. Rudra, P. K. Dubey, C. S. Jutla, V. Kumar, J. R. Rao, and P. Rohatgi, “Efficient implementation of Rijndael encryption with composite field arithmetic,” in Proc. CHES 2001, Paris, France, May 2001, pp. 171–184. [15] G. P. Saggese, A. Mazzeo, N. Mazocca, and A. G. M. Strollo, “An FPGA based performance analysis of the unrolling, tiling and pipelining of the AES algorithm,” in Proc. FPL 2003, Portugal, Sept. 2003.
AES於2001年11月成為美國聯邦資訊處理標準(FIPS) ,至今已經有許多不同的硬體實現方式應用於ASIC 與FPGA。但如何根據不同的使用
需求找出適合的設計方式,就成為一項重要的課題。使用複合場運算的SubBytes /InvSubBytes 轉換,可以減少對面積的需求與硬體複雜度。在本篇論文中,我們試著簡化K.K. Parhi所提出的SubBytes 轉換複合場架構。同時,在鑰匙排程單元中我們修改部分的off-line 鑰匙排程架構。如此一來在面積與硬體複雜度上都有顯著的減少。
此外,我們以FPGA 晶片實現全管線式架構的AES 加密處理器。並
且同時使用內含7 階回合單元的內部回合(inner-round) 與外部回合
(outer-round)管線技術,在non-feedback 模式下使用Xilinx XC2VP20-7 晶片,資料處理量可達31.34 Gbits/s。以相同的throughput/slice 來看,面積成本比起K.K. Parhi 所提出的架構減少了15%。

The Advanced Encryption Standard was accepted as a FIPS standard in November 2001. Since then, there have been many different hardware implementations for ASIC and FPGA. But how to find out the suitable design according to the demand has become an important topic. In this thesis, composite
field arithmetic of the SubBytes/InvSubBytes transformation is employed to reduce the area requirements and the hardware complexity. We try to reduce the composite field architecture of the SubByte transformation which proposed by
K.K. Parhi. Meanwhile, in the key scheduling unit, we modify parts of the offline key scheduling architecture. This way the area and hardware complexity are reduced significantly. Moreover, we implement the architecture of a fully pipelined AES encryption processor on a single chip FPGA. By using inner-round and outer-round pipelining techniques with 7 substages in each round unit can achieve a through- put of 31.34 Gbps on a Xilinx XC2VP20-7 device in non-feedback modes. The area cost is reduced by 15% in terms of equivalent throughput/slice than the architecture, which proposed by K.K. Parhi.
其他識別: U0005-2607200614273100
Appears in Collections:電機工程學系所

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