Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/7008
標題: 在可程式化邏輯陣列上實現高速循環式與全管線式AES加解密硬體模組
FPGA Implementations of High Speed Sequential and Fully Pipelining AES Modules
作者: 黃俊魁
Huang, Jun-Kui
關鍵字: AES(advanced encryption standard);先進加密標準;FPGA;Sequential;Fully pipelining;循環式;全管線式
出版社: 電機工程學系所
引用: [1] William Stallings, “Cryptography and Network Security”, Prentice-Hall, 2003 [2]“Advanced Encryption Standard (AES)” Federal Information Processing Standards Publication 197, Nov. 26, 2001. [3] H. Li “A New CAM Based S/S-1-Box Look-up Table in AES”, IEEE Circuits and Systems, vol 5, pp.4634 - 4636, 2005. [4] R. Sever, A.N. Ismailglu, Y.C. Tekmen, M. Askar and B. Okcan, “A high speed FPGA implementation of the Rijndael algorithm” Digital System Design, 2004. DSD 2004. Euromicro Symposium on 31 Aug.-3 Sept. 2004 Page (s):358 - 362 [5] N. Sklavos and O. Koufopavlou, “Architectures and VLSI implementations of the AES-Proposal Rijndael” Computers, IEEE Transactions on Volume 51, Issue 12, Dec. 2002 Page(s):1454 - 1459 [6] A. Hodjat, I. Verbaushede, “A 21.54 Gbits/s fully pipelined AES processor on FPGA”, On Field- Programmable Custom Computing Machines 2004. [7] Shuenn-Shyang Wang and Wan-Sheng Ni, “An efficient FPGA implementation of advanced encryption standard algorithm” Circuits and Systems, 2004. ISCAS ''04. Proceedings of the 2004 International Symposium on Volume 2, 23-26 May 2004 Page(s):II - 597-600 Vol.2 [8] H. Li and J. Li “A High Performance Sub-Pipelined Architecture for AES”, Computer Design, 2005 Proceedings pp:491-496 [9] D. Kotturi, Seong-Moo Yoo, and J. Blizzard “AES Crypto Chip Utilizing High-Speed Parallel Pipelined Architecture”, IEEE Circuits and System Vol.5, pp.4653 - 4656, 2005. [10] William Stallings “Cryptography and Network Security PRINCIPLES AND PRACTICES Third Edition”, 2003. [11] N.A Saqib, F. Rodriguez-Henriquez and A. Diaz-Perez, “AES algorithm implementation - an efficient approach for sequential and pipeline architectures”,Computer Science, 2003. ENC 2003. Proceedings of the Fourth Mexican International Conference on 8-12 Sept. 2003 Page(s):126 - 130 [12] C. Chitu, D. Chien, C. Chien, I. Verbauwhede and F. Chang, “A hardware implementation in FPGA of the Rijndael algorithm”, Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on Volume 1, 4-7 Aug. 2002 Page(s):I - 507-10 vol.1 [13] D. Kotturi, Seong-Moo Yoo, J. Blizzard, “AES crypto chip utilizing high-speed parallel pipelined architecture”, Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on 23-26 May 2005 Page(s):4653 - 4656 Vol. 5 [14] A. Hodjat, I. Verbauwhede, “A 21.54 Gbits/s fully pipelined AES processor on FPGA”, Field-Programmable Custom Computing Machines, 2004. FCCM 2004. 12th Annual IEEE Symposium on 20-23 April 2004 Page (s):308 - 309 [15] Xinmiao Zhang; K.K. Parhi, “High-speed VLSI architectures for the AES algorithm”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Volume 12, Issue 9, Sept. 2004 Page(s):957 - 967 [16] G. P. Saggese, A. Mazzeo, N. Mazocca, and A. G. M. Strollo, “An FPGA based performance analysis of the unrolling, tiling and pipelining of the AES algorithm,” in Proc. FPL 2003, Portugal, Sept. 2003. [17] Y. Mitsuyama, M. Kimura, T. Onoye, I. Shirakawa, “Embedded architecture of IEEE802.11i cipher algorithms”, Consumer Electronics, 2004 IEEE International Symposium on Sept. 1-3, 2004 Page (s):241 - 246 [18] F. Gurkaynak, D. Hug, and H. Kaeslin, “A 2 Gb/s Balanced AES Crypto-Chip Implementation”, GLSVLSI 2004. [19] Joon Hyoung Shim, Dae Won Kim, Young Kyu Kang, Taek Won Kwon, Jun Rim Choi, “A Rijndael cryptoprocessor using shared on-the-fly key scheduler”, ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on 6-8 Aug. 2002 Page(s):89 - 92. [20] http://csrc.nist.gov/wireless/S10_802.11i%20Overview- jw1.pdf [21] http://crypto.ee.ncku.edu.tw/class/crypto/93/Ch4- Ch5.pdf
摘要: 
隨著無線網路的普及,資料的保密也就越來越受到重視,在2001年NIST(National Institute of Standards and Technology)公開發表進階加解密的標準(AES)成為新的加解密標準,並且使用在IEEE所訂立的802.11i標準裡的CCMP通訊協定,在CCMP通訊協定下必須使用相當多的AES模組,而資料傳輸越來越頻繁的情況下,為了讓處理資料量能有效的提昇,所以增加AES模組速度是相當重要的。
本篇論文主要是以速度來考量,我們使用Xilinx公司提供的可重複程式規劃之可程式化邏輯陣列(FPGA)平台來實現AES加解密晶片,我們提出新的SubBytes(S-box)模組硬體架構,它可以在AES模組上達到高速的需求,並針對AES模組設計出三種不同的架構,並搭配管線化可提高每秒資料總處理量(Throughput),在循環式(Sequential)架構上,每秒資料總處理量可達到0.876 Gbps,在多回合管線式(Multi-round pipelining)架構上,每秒資料總處理量可達到1.48 Gbps,在全管線式(Fully pipelining)架構上,每秒資料總處理量可以達到32 Gbps。

Due to the universal applications of wireless networks, the security of data becomes more and more important. Nation Institute of standards and Technology (NIST) was announced an advanced encryption standard (AES) to become the new encryption and decryption standard, which has been used in CCMP communication protocol for the IEEE 802.11i standard. The IEEE 802.11i standard must use many AES modules in CCMP communication protocol, and apply to more and more data transmission circumstances. In order to increase throughputs effectively, increasing speed for AES module is very important.
In this thesis, the major consideration is the high speed application. We implement the AES encryption and decryption chip with the Xilinx Field programmable Gate Arrays (FPGA) chips. We propose a novel hardware architecture for the implementation of SubBytes (S-box) module. The SubBytes (S-box) module can achieve the high speed process in AES module. Then we design three different pipelining architectures that can increase throughputs in AES module. In sequential architecture, the throughput rate can reach to 0.876 Gbps. In multi-round pipelining architecture, the throughput rate can reach to 1.48 Gbps. In full pipelining architecture, the throughput rate can reach to 32 Gbps.
URI: http://hdl.handle.net/11455/7008
其他識別: U0005-2607200615262900
Appears in Collections:電機工程學系所

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