Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/70422
標題: Performance modeling and analysis of parallel packet switches with piao queues
作者: Liu, C.L.
Tsaur, D.J.
Wu, C.C.
Lin, W.
關鍵字: parallel packet switch;shared-memory based packet switch;Markov chain;push-in arbitrary-out queues
Project: Journal of the Chinese Institute of Engineers
期刊/報告no:: Journal of the Chinese Institute of Engineers, Volume 30, Issue 4, Page(s) 689-701.
摘要: 
When buffer resources are deployed in the switch, shared-memory based packet switches are known to supply the best possible performance for bursty data traffic in networks and the Internet. Nevertheless, scaling of shared-memory packet switches to larger sizes has been limited and then packets can not be processed in a high speed network chiefly because of the physical restrictions imposed by the memory operation rate and the centralized strategy for switching functions in shared-memory switches. In this investigation, a scalable switch for a high speed network, which is called the parallel packet switch (PPS), is studied to overcome these constraints. The PPS comprises multiple packet switches operating independently and in parallel. The PPS-class is characterized by the deployment of parallel center-stage switches with memory buffers running slower than the external line rate. Each lower speed packet switch operates at a fraction of the external line rate R. For example, each packet switch can operate at an internal line rate R/K, where K is the number of center-stage switches. This study develops and investigates a PPS which distributes cells or variable-length packets to low-speed switches and uses outputs with push-in arbitrary-out (PIAO) queues. We present a novel Markov chain model that successfully analyzes and exhibits PPS performance characteristics for throughput, cell delay and cell drop rate. Simulation comparison demonstrates that the developed Markov chain model is accurate for practical network loads and the PPS with PIAO queues provides considerably better performance than previously known classes of shared-memory switch architecture.
URI: http://hdl.handle.net/11455/70422
ISSN: 0253-3839
DOI: 10.1080/02533839.2007.9671295
Appears in Collections:期刊論文

Show full item record
 

Google ScholarTM

Check

Altmetric

Altmetric


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.