Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/7074
標題: 利用相位補償非整數鎖相迴路技術實現之展頻時脈產生器
A Spread-Spectrum Clock Generator Using a Phase-Compensation Fractional Phase-Locked Loop Technique
作者: 翁文格
Wong, Wen-Ger
關鍵字: spread-spectrum clock generator;展頻時脈產生器;phase-compensation;phase-locked loop;delay-locked loop;相位補償;鎖相迴路;延遲鎖定迴路
出版社: 電機工程學系所
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摘要: 
在本篇論文中,展頻時脈產生器(SSCG)利用相為補償非整數鎖相迴路技術得以實現。展頻時脈產生器是一種基於頻率調變用來效除電磁干擾(EMI)的技術。相位補償技術是一種真實非整數除數鎖相迴路不同於一般常見的三角積分的平均式非整數鎖相迴路。此種技術有效的改善量化誤差所造成的非整數刺能(fractional spurs)。此種技術需要週期相同但具有多個相位的訊號。而如何製造出補償相位是本技術的重點。本論文中提供兩種方法來完成分別對應不同的壓控振盪器。在此兩種方法實現的展頻時脈產生器其振盪頻率為3.0GHz,且其頻率向下延展0.5%藉由30~33KHz的三角波調變達成。調變方式為藉由調變鎖相迴路中的除數達到頻率延展的功能。
第一種方法採用相位內插技術適用於環型振盪器,利用環型振盪器多相位輸出的優點,採取內插技術取代延遲迴路產生相位補償。在環型振器中採用雙迴路的延遲迴路技術,用以提升震盪頻率。利用TSMC 0.18um標準CMOS製程做模擬,在1.8V電壓操作下功率消耗為50mW,晶片面積為0.95*0.85mm2。
第二種方法採用改良式延遲鎖相迴路適用於電感電容式,改良式鎖相迴路改善傳統相位補償技術中延遲迴路無法提供過小的相位補償。其具有電路實現及量測,採用TSMC 0.18um 標準CMOS製程,在1.8V的操作下功率消耗為55mW,晶片面積為1.4*1.4mm2,在2.4GHz無展頻的情況下峰對峰抖動(Jitter)為10ps,具展頻的情下峰對峰劇跳為90ps,在展頻電磁干擾的消減約為12db。

In this thesis, spread-spectrum clock generator SSCG) is realized with phase-compensation fractional PLL. SSCG is a technique to diminish Electromagnetic Interference (EMI) base on frequency modulation. Phase-Compensation fractional PLL is a different kind of true fractional PLL with averaging fractional PLL using D-S modulator architecture. This technique can minimum generating of quantization error which makes fractional spurs. Phase-Compensation technique needs multiphase signals which periods are equal. The focus of the technique is how to generate the phase for compensation. In this thesis provides two methods for two different VCO. The EMI reduction is 12 dB. SSCG with both methods clocks at 3.0GHz and it's frequency down spread 0.5% with 30~33-KHz triangular waveform. The modulated method is modulating the divisor of the PLL to accomplish the spread-spectrum function.
The first method is accomplished with phase interpolation technique for ring oscillator. Taking advantage of multi-phase generated by ring oscillator, it is adopted with interpolation technique replacing delay-locked loop which generates phase compensation. Because of the high speed operating, the ring oscillator is accepted with dual delayed loop technique. It is simulated by TSMC 0.18-um standard CMOS technology and power dissipation is about 50-mW under 1.8-V supply voltage. The chip area is 0.95*0.85mm2.
The second method is realized with improving DLL for LC-tank VCO. The improving DLL solves the problem of phase compensation too small to be offered by conventional DLL. There are chip and measurement in this thesis. It is fabricated with a 0.18-um standard CMOS technology and power dissipation is about 55-mW under a 1.8-V supply voltage. The chip area is 1.4*1.4mm2. The peak-peak jitter without SSCG is 10ps at 2.4GHz and with SSCG is 90ps.
URI: http://hdl.handle.net/11455/7074
其他識別: U0005-2808200601543900
Appears in Collections:電機工程學系所

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