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A Spread-Spectrum Clock Generator Using a Phase-Compensation Fractional Phase-Locked Loop Technique
|關鍵字:||spread-spectrum clock generator;展頻時脈產生器;phase-compensation;phase-locked loop;delay-locked loop;相位補償;鎖相迴路;延遲鎖定迴路||出版社:||電機工程學系所||引用:|| Floyd M. Gardner, Phasslock Techniques ,3rd ed. , WIEY, 2005.  H. Huh and Y. Koo, “Comparison Frequency Doubling and Charge Pump Matching Techniques for Dual-Band ΔΣ Fractional-N Frequency Synthesizer,” IEEE J. Solid-State Circuits, vol. 40, no. 11, November 2005.  B. Miller and R. J. Conley, “A Multiple Modulator Fractional Divider, IEEE Transactions on Instrumentation and Measurement,” vol. 40, no. 3, June 1991.  J. Lee, “A 3-to-8-GHz Fast-Hopping Frequency Synthesizer in 0.18-um CMOS Technology,” IEEE J. Solid-State Circuits, vol. 41, no. 3, March 2006.  B. Bornoosh, A. Afzali-Kusha, R. Dehghani, M. Mehrara, S.M. Atarodi and M. Nourani, “Reduced complexity 1-bit high-order digital delta-sigma modulator for low-voltage fractional-N frequency synthesis applications,” IEE Proc.-Circuits Devices Syst, vol. 152, no. 5, October 2005.  S.E. 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第二種方法採用改良式延遲鎖相迴路適用於電感電容式，改良式鎖相迴路改善傳統相位補償技術中延遲迴路無法提供過小的相位補償。其具有電路實現及量測，採用TSMC 0.18um 標準CMOS製程，在1.8V的操作下功率消耗為55mW，晶片面積為1.4*1.4mm2，在2.4GHz無展頻的情況下峰對峰抖動(Jitter)為10ps，具展頻的情下峰對峰劇跳為90ps，在展頻電磁干擾的消減約為12db。
In this thesis, spread-spectrum clock generator SSCG) is realized with phase-compensation fractional PLL. SSCG is a technique to diminish Electromagnetic Interference (EMI) base on frequency modulation. Phase-Compensation fractional PLL is a different kind of true fractional PLL with averaging fractional PLL using D-S modulator architecture. This technique can minimum generating of quantization error which makes fractional spurs. Phase-Compensation technique needs multiphase signals which periods are equal. The focus of the technique is how to generate the phase for compensation. In this thesis provides two methods for two different VCO. The EMI reduction is 12 dB. SSCG with both methods clocks at 3.0GHz and it's frequency down spread 0.5% with 30~33-KHz triangular waveform. The modulated method is modulating the divisor of the PLL to accomplish the spread-spectrum function.
The first method is accomplished with phase interpolation technique for ring oscillator. Taking advantage of multi-phase generated by ring oscillator, it is adopted with interpolation technique replacing delay-locked loop which generates phase compensation. Because of the high speed operating, the ring oscillator is accepted with dual delayed loop technique. It is simulated by TSMC 0.18-um standard CMOS technology and power dissipation is about 50-mW under 1.8-V supply voltage. The chip area is 0.95*0.85mm2.
The second method is realized with improving DLL for LC-tank VCO. The improving DLL solves the problem of phase compensation too small to be offered by conventional DLL. There are chip and measurement in this thesis. It is fabricated with a 0.18-um standard CMOS technology and power dissipation is about 55-mW under a 1.8-V supply voltage. The chip area is 1.4*1.4mm2. The peak-peak jitter without SSCG is 10ps at 2.4GHz and with SSCG is 90ps.
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