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Study on the Characteristics Improvement of GAA MNCs Poly-Si TFTs with Vacuum Cavity and LDD Structures
|關鍵字:||vacuum cavity structure;真空空腔架構;gate-all-around;nanowire;lightly-doped-drain;環繞式閘極;奈米線;輕汲極摻雜||出版社:||電機工程學系所||引用:||[1.1] Kaustav Banerjee, Shukri J. Souri, Pawan Kapur and Krishna C. Saraswat, “3-D ICs: A Novel Chip Design For Improving Deep-Submicrometer Interconnect Performance and System-on-Chip integration”, Proceedings of the IEEE, Vol. 89, no. 5, pp.602-633, May 2001. [1.2] Bing-Yoe Tsui, Chia-Pin Lin, Chih-Feng Huang and Yi-Hsuan Xiao, “ 0.1μm Poly-Si Thin Film Transistors for System-on-Pannel (SOP) Applications ”, IEDM Tech. Dig. pp.911-914, December 2005. [1.3] Toshiyuki Sameshima, Masaki Hara and Setsuo Usui, “ XeCl Excimer Leaser Annealing Used to Fabricate Poly-Si TFT's ”, Japanese Journal of Applied Physics, Vol.28, no. 10, pp.1789-1793, October 1989. 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In this thesis, we utilize sidewall spacer technique to form multiple nanowire channels (MNCs) without any advanced lithography equipment. Furthermore, suspending multiple nanowire channels are formed by wet etching sacrificial SiO2 to establish the gate-all-around (GAA) structure. Finally, the vacuum cavity structure is formed by selective wet etching under the surrounding gate edges near source and drain. And then, the lowest permittivity material in nature (vacuum) is encapsulated into cavity by PECVD passvation. The lightly doped drain (LDD) structure is formed by the Si3N4 spacer near source and drain with one time ion implantation.Therefore, the GAA MNCs TFTs with the vacuum cavity and LDD structure are successfully fabricated , respectively and exhibit excellent electrical characteristics.
As compared with conventional planar TFTs, the proposed device has steeper subthreshold swing from0.56 V/dec to 0.42 V/dec、lower threshold voltage from2.7 V to2.06 V、higher ION/IOFF drain current ratio from0.86×107 to3.8×107 and smaller drain induce barrier lowing (DIBL) from 0.289 V/V to 0.256 V/V. GAA MNCs TFTs with different length vacuum cavity 0.35μm and 0.7μm, although slightly increased threshold voltage 2.1 V、2.48 V, respectively, but the leakage current at Gate voltage is -7 V, from 7.38×10-9 A reduces to 1.61×10-9 A and 5.24 × 10-9 A, respectively and a larger Ion / Ioff current ratio from 5.46×107 to upgrade to 3.81×107, and the GAA MNCs TFTs with LDD the leakage current reduces to 1.05 ×10-9A and the Ion / Ioff current ratio increases to 4.71×107.
In addition, we further study the reliability of GAA MNCs TFTs under hot carrier stress and dynamic gate bias stress with different frequency. the reliability of GAA MNCs TFTs degrade severely than that of planar TFTs due to the sharp corners.The reliability of GAA MNCs TFTs with vacuum cavity and LDD structures can be obviously improved after hot carrier stress or dynamic gate bias stress.The effective thicker gate insulator resulting from the vacuum cavity is the main reason to reduce both of the lateral and vertical electric field in the channel near drain region.
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