Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/7083
標題: FPGA 設計與實作高硬體效能的H.264/AVC 轉換與量化處理器
FPGA design and implementation for high efficiency transform and quantization engine of H.264/AVC
作者: 鄭煜霖
Cheng, Yu-Lin
關鍵字: 轉換;h.264;量化
出版社: 電機工程學系所
引用: [1] T. Wiegand and G. Sullivan, Draft ITU-T recommendation and final draft international standard of joint video specification (ITU-T rec. H.264 ISO/IEC 14496-10 AVC, presented at Joint Video Team (JVC) of ISO/IEC MPEG and ITU-T VCEG. [2] lain E. G. Richardson, H.264 and MPEG-4 Video Compression - Video Coding for Next-generation Multimedia, John Wiley & Sons Ltd, 2003. [3] Kordasiewicz, R.C.; Shirani, S.,”ASIC and FPGA implementations of H.264 DCT and quantization blocks”, IEEE International Conference on Image Processing, 2005. ICIP 2005, Vol.3, no.11, pp.III-1020-3, Sept. 2005 [4] Chih-Peng Fan ,”Fast 2-dimensional 4 /spl times/ 4 forward integer transform implementation for H.264/AVC”, IEEE Trans. on Circuits and Systems II: Express Briefs , Vol.53, Issue 3, pp.174-177, March 2006 [5] Chih-Peng Fan; Yu-Lin Cheng ,”Unified and fast 2-dimensional 4/spl times/4 transform design for H.264/AVC texture coding”, Intelligent Signal Processing and Communication Systems, 2005. ISPACS 2005. Proceedings of 2005 International Symposium on, vol.13-16, pp.473-476, Dec. 2005 [6] Raja, G.; Khan, S.; Mirza, M.J.,”VLSI Architecture & Implementation of H.264 Integer Transform”, Microelectronics, 2005. ICM 2005. The 17th International Conference on ,vol.13-15, pp.218-223, Dec. 2005. [7] Heng-Yao Lin; Yi-Chih Chao; Che-Hong Chen; Bin-Da Liu; Jar-Ferr Yang, “Combined 2-D transform and quantization architectures for H.264 video coders”, IEEE International Symposium on Circuits and Systems, 2005. ISCAS 2005. Vol. 2, pp.1802-1805, May 2005 [8] Kordasiewicz, R.; Shirani, S.,”Hardware implementation of the optimized transform and quantization blocks of H.264”, Canadian Conference on Electrical and Computer Engineering, 2004,Vol. 2, pp.943-946,May 2004 [9]Tuanjie Qian; Jun Sun; Dian Li; Yang, X.; Jia Wang ,”Transform domain transcoding from MPEG-2 to H.264 with interpolation drift-error compensation”, IEEE Trans. Circuits and Systems for Video Technology, Vol. 16, Issue 4, pp.523-534, April 2006
摘要: 
H.264/AVC是最新一代的視訊壓縮標準,相較於以往的視訊標準提供了更高的壓縮效能,在相同的壓縮比率下提供更好的影像品質,但所付出的代價即為造成編碼端複雜度的大量提升,以及增加硬體實現的困難度。
本文中針對H.264的整數轉換與量化來做探討,在整數轉換的部份利用 Kroneckor product 運算元的演算方式來實現二維整數轉換,其中包括正轉換(forward transform)、反轉換(inverse transform) 與 Hadamard 轉換。在量化則採用CSD (Canonic Signed Digit)的方式來完成乘法器的硬體架構,此方式不僅大幅減少乘法器的硬體面積,同時也提升了量化的處理速度。最後結合整數轉換與量化,透過不同的硬體架構組合,找到最佳的硬體結構,可同時兼具面積與效能的優勢,並且達到H.264編碼端可及時處理HDTV 1920x1080@30Hz的影像規格。

H.264/AVC is the newest video coding standard. The H.264 video coding standard can achieve considerably higher coding efficiency than the previous standards, which means that the H.264/AVC can provide better image quality at the same coding rate. However, the utilization of H.264/AVC comes at a cost in considerably increased complexity at the encoder and thus increases the difficulty in hardware implementations.
In the thesis, we focus on the transforms and quantizations of the H.264. For developing the fast algorithms of the transforms, we use the Kroneckor product to derive the fast algorithm of 2-D integer transforms, which include the forward integer transform, the inverse integer transform and the Hadamard transform. For developing the quantization hardware, we use the CSD (canonic signed digit) method instead of the traditional multiplier hardware architecture. The CSD multiplier not only reduces much hardware cost in multiplications, but also improves the quantization performance. At last, we try to integrate the integer transform and quantization into a module. Due to using and comparing many different types of the architecture to build the texture engine, we find the best architecture for our implementations. The proposed hardware can take advantages of the hardware cost and performance. The proposed hardware design can achieve the real-time processing for H.264 video encoder targeting at HDTV 1920x1080 format video@30Hz.
URI: http://hdl.handle.net/11455/7083
其他識別: U0005-2906200611101300
Appears in Collections:電機工程學系所

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