Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/7083
DC FieldValueLanguage
dc.contributor夏世昌zh_TW
dc.contributor黃穎聰zh_TW
dc.contributor王欣平zh_TW
dc.contributor.advisor范志鵬zh_TW
dc.contributor.author鄭煜霖zh_TW
dc.contributor.authorCheng, Yu-Linen_US
dc.contributor.other中興大學zh_TW
dc.date2007zh_TW
dc.date.accessioned2014-06-06T06:39:29Z-
dc.date.available2014-06-06T06:39:29Z-
dc.identifierU0005-2906200611101300zh_TW
dc.identifier.citation[1] T. Wiegand and G. Sullivan, Draft ITU-T recommendation and final draft international standard of joint video specification (ITU-T rec. H.264 ISO/IEC 14496-10 AVC, presented at Joint Video Team (JVC) of ISO/IEC MPEG and ITU-T VCEG. [2] lain E. G. Richardson, H.264 and MPEG-4 Video Compression - Video Coding for Next-generation Multimedia, John Wiley & Sons Ltd, 2003. [3] Kordasiewicz, R.C.; Shirani, S.,”ASIC and FPGA implementations of H.264 DCT and quantization blocks”, IEEE International Conference on Image Processing, 2005. ICIP 2005, Vol.3, no.11, pp.III-1020-3, Sept. 2005 [4] Chih-Peng Fan ,”Fast 2-dimensional 4 /spl times/ 4 forward integer transform implementation for H.264/AVC”, IEEE Trans. on Circuits and Systems II: Express Briefs , Vol.53, Issue 3, pp.174-177, March 2006 [5] Chih-Peng Fan; Yu-Lin Cheng ,”Unified and fast 2-dimensional 4/spl times/4 transform design for H.264/AVC texture coding”, Intelligent Signal Processing and Communication Systems, 2005. ISPACS 2005. Proceedings of 2005 International Symposium on, vol.13-16, pp.473-476, Dec. 2005 [6] Raja, G.; Khan, S.; Mirza, M.J.,”VLSI Architecture & Implementation of H.264 Integer Transform”, Microelectronics, 2005. ICM 2005. The 17th International Conference on ,vol.13-15, pp.218-223, Dec. 2005. [7] Heng-Yao Lin; Yi-Chih Chao; Che-Hong Chen; Bin-Da Liu; Jar-Ferr Yang, “Combined 2-D transform and quantization architectures for H.264 video coders”, IEEE International Symposium on Circuits and Systems, 2005. ISCAS 2005. Vol. 2, pp.1802-1805, May 2005 [8] Kordasiewicz, R.; Shirani, S.,”Hardware implementation of the optimized transform and quantization blocks of H.264”, Canadian Conference on Electrical and Computer Engineering, 2004,Vol. 2, pp.943-946,May 2004 [9]Tuanjie Qian; Jun Sun; Dian Li; Yang, X.; Jia Wang ,”Transform domain transcoding from MPEG-2 to H.264 with interpolation drift-error compensation”, IEEE Trans. Circuits and Systems for Video Technology, Vol. 16, Issue 4, pp.523-534, April 2006zh_TW
dc.identifier.urihttp://hdl.handle.net/11455/7083-
dc.description.abstractH.264/AVC是最新一代的視訊壓縮標準,相較於以往的視訊標準提供了更高的壓縮效能,在相同的壓縮比率下提供更好的影像品質,但所付出的代價即為造成編碼端複雜度的大量提升,以及增加硬體實現的困難度。 本文中針對H.264的整數轉換與量化來做探討,在整數轉換的部份利用 Kroneckor product 運算元的演算方式來實現二維整數轉換,其中包括正轉換(forward transform)、反轉換(inverse transform) 與 Hadamard 轉換。在量化則採用CSD (Canonic Signed Digit)的方式來完成乘法器的硬體架構,此方式不僅大幅減少乘法器的硬體面積,同時也提升了量化的處理速度。最後結合整數轉換與量化,透過不同的硬體架構組合,找到最佳的硬體結構,可同時兼具面積與效能的優勢,並且達到H.264編碼端可及時處理HDTV 1920x1080@30Hz的影像規格。zh_TW
dc.description.abstractH.264/AVC is the newest video coding standard. The H.264 video coding standard can achieve considerably higher coding efficiency than the previous standards, which means that the H.264/AVC can provide better image quality at the same coding rate. However, the utilization of H.264/AVC comes at a cost in considerably increased complexity at the encoder and thus increases the difficulty in hardware implementations. In the thesis, we focus on the transforms and quantizations of the H.264. For developing the fast algorithms of the transforms, we use the Kroneckor product to derive the fast algorithm of 2-D integer transforms, which include the forward integer transform, the inverse integer transform and the Hadamard transform. For developing the quantization hardware, we use the CSD (canonic signed digit) method instead of the traditional multiplier hardware architecture. The CSD multiplier not only reduces much hardware cost in multiplications, but also improves the quantization performance. At last, we try to integrate the integer transform and quantization into a module. Due to using and comparing many different types of the architecture to build the texture engine, we find the best architecture for our implementations. The proposed hardware can take advantages of the hardware cost and performance. The proposed hardware design can achieve the real-time processing for H.264 video encoder targeting at HDTV 1920x1080 format video@30Hz.en_US
dc.description.tableofcontents中文摘要…………………………………………………………i 英文摘要………………………………………………………...ii 誌謝……………………………………………………………..iii 目次……………………………………………………………..iv 表目錄…....…………………………………………………….vii 圖目錄………………………………………………………....viii 一、 H.264/AVC 簡介 …………………………………………1 1.1 H.264之演進 …………………………………………………………1 1.2 H.264之概述 …………………………………………………………2 1.3 H.264技術說明 ………………………………………………………3 1.4位元流的組成方式 ……………………………………………………4 1.5框內預測和編碼(Intra Prediction and Coding)………………5 1.6框間預測和編碼(Inter Prediction and Coding)………………7 1.7區塊大小 ………………………………………………………………8 1.8移動估算的精準度 ……………………………………………………9 1.9多重參考畫面選擇 ……………………………………………………9 1.10消除區塊(迴路)濾波器……………………………………………9 1.11整數轉換 ……………………………………………………………10 1.12量化和轉換係數掃描 ………………………………………………10 1.13熵編碼(Entropy Coding) ………………………………………11 1.14 UVLC/CAVLC …………………………………………………………11 1.15 H.264 Profiles ……………………………………………………12 1.15.1 Baseline Profile……………………………………………13 1.15.1.1任意切片順序(Arbitrary Slice Ordering)……13 1.15.1.2彈性巨集區塊順序(Flexible Macroblock Ordering;FMO)………………………………………………………………13 1.15.1.3冗餘切片………………………………………………13 1.15.2 Main Profile…………………………………………………13 1.15.2.1 B-畫面 ………………………………………………13 1.15.2.2加權預測(weighted prediction) ………………14 1.15.2.3 情境適應性可變長度編碼(CABAC)…………………14 1.16 應用………………………………………………………………… 14 1.16.1 視訊會議 ……………………………………………………14 1.16.1.1視訊會議產業之挑戰…………………………………15 1.16.2 廣播視訊…………………………………………………… 16 1.16.2.1廣播視訊產業之挑戰…………………………………16 二、 H.264標準中的轉換與量化…………………………… 18 2.1 轉換與量化之簡介 ………………………………………………… 18 2.2 4x4殘值區塊的轉換與量化(blocks 0-15, 18-25) ………………20 2.3 4x4離散餘弦轉換 ……………………………………………………21 2.4 量化(Quantization) ……………………………………………… 25 2.5 重置比例縮放(Rescaling)………………………………………… 29 2.6 4x4 亮度直流係數之轉換與量化(16x16 Intra-mode only)………30 2.7 2x2 彩度直流係數之轉換與量化……………………………………31 2.8 完整的轉換、量化、反量化與返轉換的處理流程…………………32 三、 轉換功能的硬體實現……………………………………34 3.1傳統方式的硬體實現…………………………………………………34 3.2 快速整數離散餘弦轉換(fast integer DCT)………………………34 3.3逆向整數離散餘弦轉換(inverse fast intege DCT)……………38 3.4 Hadamard 轉換……………………………………………………… 40 3.5轉換與整合……………………………………………………………42 3.5.1 fast integer DCT與Hadamard轉換的整合……………… 44 3.5.2 inverse fast integer DCT與Hadamard轉換的整合…… 44 3.5.3 fast integer DCT 、inverse fast integer DCT與 Hadamard轉換的整合……………………………………………46 3.6 Enhance fast integer transform…………………………………49 四、 量化器硬體實現…………………………………………57 4.1 Encode Texture架構的規劃 ………………………………………57 4.2 量化演算法的架構分析 …………………………………………… 57 4.3 量化架構的硬體實現 ……………………………………………… 58 五、 Texture engine硬體架構與效能比較…………………62 5.1 模組整合前提 ……………………………………………………… 62 5.2 轉換與量化的整合架構 …………………………………………… 62 5.3 硬體效能比較 ……………………………………………………… 65 5.4 探討 ………………………………………………………………… 67 六、 結論………………………………………………………70 參考文獻 ………………………………………………………71zh_TW
dc.language.isoen_USzh_TW
dc.publisher電機工程學系所zh_TW
dc.relation.urihttp://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-2906200611101300en_US
dc.subject轉換zh_TW
dc.subjecth.264en_US
dc.subject量化zh_TW
dc.titleFPGA 設計與實作高硬體效能的H.264/AVC 轉換與量化處理器zh_TW
dc.titleFPGA design and implementation for high efficiency transform and quantization engine of H.264/AVCen_US
dc.typeThesis and Dissertationzh_TW
item.openairecristypehttp://purl.org/coar/resource_type/c_18cf-
item.openairetypeThesis and Dissertation-
item.cerifentitytypePublications-
item.fulltextno fulltext-
item.languageiso639-1en_US-
item.grantfulltextnone-
Appears in Collections:電機工程學系所
Show simple item record
 

Google ScholarTM

Check


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.