Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/7093
標題: 應用於晶片匯流排通訊之保證頻寬且低延遲的改良式彩票演算法仲裁器設計及實作
A Bandwidth Guaranteed and Low Latency Lottery-based Arbiter Design for On-Chip Bus Communication
作者: 姚曉輝
Yao, Hsiao-Hui
關鍵字: Bus Arbiter;匯流排仲裁器;Lottery based;Bandwidth Guarantee;Low Latency;彩票基礎;頻寬保證;低延遲
出版社: 電機工程學系所
引用: 中文參考書目 [1] 吳正琪, “運用高效能仲裁器之AMBA AHB BUS設計, ” 義守大學電子工程學系碩士論文, 2002. [2] 劉智峰, “可規劃之系統單晶片仲裁器設計, ” 義守大學電子工程學系碩士論文, 2003. 西文參考書目 [3] M. Keating, P. Bricaud, Russell, “Reuse Methodology Manual for System-On-A-Chip Designs 3rd Edition” Kluwer Academic Publ,2002. [4] C. H. Pyoun, C. H. Lin, H. S. Kim, and J. W. Chong, ”The Efficient Bus Arbitration Scheme In Soc Environment”The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications,pp.311-315,2003. [5] K. Lahiri, A. Raghunathan, and G. Lakshiminarayan,“LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs” Design Automation Conference,pp. 15-20,2001. [6] K. Lahiri, A. Raghunathan, and S. Dey.,“Performance Analysis of Systems with Multi-Channel Communication Architectures”International Conference on VLSI Design,pp.530-537,Jan.2000. [7] K. Lahiri, A. Raghunathan, and S. Dey., “Evaluation of the Traffic Performance Characterization of System-on-Chip Communication Architectures”International Conference on VLSI Design,pp.29-35,Jan.2001. [8] A.C Waldspurger and W.E Weih, “Lottery Scheduling :Flexible Proportional Share Resource Management,” Symp. on Operating Systems Design and Implementation,1994. [9] E. S. Shin, V. Mooney and G. F. Riley,“Round-robin Arbiter Design and Generation”, Proceedings of International Symposium on System Synthesis (ISSS’02),pp.243-248,October.2002. [10] S. Pasricha, N. Dutt, M. Ben-Romdhane,“Fast exploration of bus-based on-chip communication architectures” International Conference on CODES +ISSS ,pp.242-247,2004. [11] C. Shin, Y.T. Kim, E. Y. Chung, K. M. Choi, J. T. Kong, S. K. Eo ,“ Fast exploration of parameterized bus architecture for communication-centric SoC design” in Proc. Design Automation and Test in Europe Conference and Exhibition pp.352-357,2004. [12] C. H. chen, J. D. Huang, G. W. Lee, and J. Y. Jou, ”A Real-Time and Bandwidth Guaranteed Arbitration Algorithm for On-Chip Bus Communication,” VLSI Desing/CAD Symposium,Taiwan,2005. [13] M. Conti, M. Caldari, G. B. Vece, S. Orcioni, C.Turchetti,“Performance analysis of different arbitration algorithms of the AMBA AHB Bus” Design Automation Conference,pp. 618-621,2004. [14]“Sonics Integration Architecture,” http://www.sonicsinc.com,Sonics Inc. [15] AMBA Specification (Rev 2.0).Document Number: ARM IHI 0011A.Issued:13th May 1999, http://www.arm.com
摘要: 
隨著積體電路製造技術的日益發展,邏輯電路日趨複雜,系統電路逐漸龐大,以往的主控單元與被動單元數目,已不能滿足現今龐大系統電路的需求。因主控單元數目的增多對於匯流排的使用會造成相當大的延遲,對於整個系統電路而言是致命的缺點,故匯流排與主控單元的仲裁器(Arbiter)之設計便顯的非常重要。
在SoC(System On Chip)匯流排上,仲裁器的角色是必要的,對於多個主控器(Master)同時對匯流排發出需求,它能決定哪一個主控器存取匯流排。因為仲裁器效能的好壞大大影響著整個SoC的整體效能,其原因在於控制主控單元使用匯流排的效率,會大大改善整個系統電路運作的速度以及降低整個晶片功率的消耗,以符合現今高速度、低功率的需求。
在本篇論文,我們提出一個兩層的靜態仲裁匯流排分配演算法,是以彩票匯流排演演算法(Lottery bus algorithm)為基礎所延伸出來,這個演算法解決掉傳統匯流排分配以及主控器有即時(real-time)需求的問題,並保證每個主控器所需的頻寬和減少主控器匯流排仲裁分配延遲。為了快速設計評估和研究這SoC匯流排是建立在一個高的抽象層級。這模擬結果表現出建議演算法在頻寬分配有著比較優秀的表現,並且減少了主控器對於被允許匯流排存取的平均延遲。

Since the integrated circuits make electrical technologies develop increasingly, the logic electric circuits are gradually complicated, and the system electric circuits gradually become huge, and then the number of master and slaver units already can''t satisfy the requirements and applications of the present huge electric circuits and system chips. Because the increasing number of master units will cause the large delay of bus requests, the bus request delay is a fatal problem for the bus communication of system chips. So, the bus arbiter design for servicing master units is very significant on the system chips. On the system-on-chip (SOC) bus, the role of arbitrating machine is essential when multiple masters issue requests for the bus access at the same time, and the bus arbiter decides which master can access the bus. The performance of the arbiter influences the whole communication efficiency of the SOC. By controlling the efficiency of bus masters for usage of the bus, the bus arbiter will improve the processing speed of the whole chip system and reduce the power consumption of whole chip to meet the present requirements for the high speed and low power applications.In the thesis, we propose the statically two-level Lottery-based bus arbitration algorithm. The proposed bus arbitration solves the problem of the conventional bus distribution, and reduces the average latency of bus requests for real-time applications, and then guarantees the bandwidth which each master needs. The SOC bus is modeled by a high abstract level for fast design and evaluation. The simulation results show that the proposed algorithm has the better performance of the bandwidth allocation, and reduces the average latency of the bus request of each master.
URI: http://hdl.handle.net/11455/7093
其他識別: U0005-2906200611120300
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