Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/7130
標題: 低複雜度Ad-hoc模式IEEE802.11a/b/g無線區域網路媒體存取控制層IP設計:傳輸器部份
Low-Complexity IEEE 802.11a/b/g Wireless LAN MAC Layer IP Design on Ad-hoc Mode : Transmitter Part
作者: 蘇斌誠
Su, Pin-Cheng
關鍵字: Low-Complexity;低複雜度
出版社: 電機工程學系
摘要: 
隨著無線通訊市場的蓬勃發展,因應需求的範圍也越來越大,無線區域網路(WLAN)也相繼發展出更新的規格,2003年IEEE802.11g的問世,使得802.11/802.11a/802.11b等早期的無線區域網路規格得以相容,因此未來無線網路不會因為使用規格上的差異,造成互不相容支援的窘境。又雖然有802.11g標準的出現,但基於相容性與市場需求等考量,未來具備兩種規格以上的無線網路電子產品成為主流的趨勢亦不容小覷[4]。
為了能在傳輸速率上有所提昇以及服務的品質質量等為改善目標,最近這幾年各種802.11協定的發展推陳出新,為了要能讓這些協定都能相容且更有效率,若是要以純硬體來實現可能會非常複雜不具彈性,我們的目標是為了能適用無線通訊的IEEE 802.11/b/a/g協定下的介質存取控制(Medium Access Control)層,我們會以ARM為嵌入式系統中的處理器(CPU),做為邏輯連結控制層(LLC: Logical Link Control)和媒介存取控制層的一個處理轉送點。
我們設計一個低複雜度且能符合802.11/b/a/g在MAC層的硬體,在硬體的架構上以最少的有限狀態機減少複雜度,以及在沒有ARM CPU或接收器部份的任何要求下,不讓硬體有任何轉換的動作,在此一狀態下,可進入休眠,即省電模式;在封包訊框的建構上也不會有太多的切換(Switching),在任何時間下都只有一個有限狀態機在運作,以上是針對低率問題而設計。資料傳送前的通道偵測中,對協定中規定的要先經DIFS時間後再經一段後退時間(Back-off Time),確定通道閒置再傳送,我們的模擬則在經DIFS時間後直接傳送資料,且實體層同時做通道偵測,若通道閒置時可免除一段後退時間的等待。另外FIFO讀資料的同時,也一併進行CRC編碼以加快訊框建構。控制訊框(RTS-CTS-ACK)使用同一塊內部記憶體。
在IEEE 802.11的MAC層中,封包分成三種:控制封包、資料封包及管理封包。我們主要把控制封包和資料封包以硬體實現,而管理封包以軟體來處理,而管理封包中的信標則例外,是由硬體處理。我們的MAC硬體設計是以MAC中必要的DCF(Distributed Coordination Function)服務功能,且DCF機制是只有在沒有AP(Access Pointer)的IBSS(Ad Hoc)無線區域網路,即無基礎架構的無線區域網路下運作。

Since the market of the wireless communication is rising and flourishing, the range of the demand for user market is also more and more huge. The specification version of the WLAN is also renewing as fast as it can. For the WLAN standards, 802.11, 802.11a and 802.11b, these earlier standards can be compatible to the IEEE 802.11g which is presented to the public in 2003. For this reason, there are no compatible issues with the diversity specifications using for WLAN in the future. Even though the 802.11g shows up, it is the trend that there will be more than two standards within the WLAN manufactures in view of the compatible and market demanding can think increasingly.
Target on the transmission rate and quality of service are the improvement goal. For compatibility, the variety of 802.11x protocols will result in increased complexity, and the specific hardware is efficient but will become not flexible. The goal of our MAC controller design can apply to the protocols of IEEE 802.11/b/a/g. We select the ARM CPU as the processor in integration of embedded system. The ARM CPU can be the role for data transmission and access between Logical Link Layer and MAC Layer.
We design a low complexity MAC Layer hardware which applies to the 802.11/b/a/g standards. We use less number of FSM to reduce the hardware complexity and the proposed MAC hardware does nothing without trigger of signals from ARM CPU or receiver part in hardware architecture. As a result of doing nothing, the MAC hardware can enter into sleeping mode or called power saving mode. The FSM operates with single state at any working time. The FSM must wait through the DIFS time and a random Back-off time before transmitting data to avoid collision described in the specification. The simulations we have done are waiting through DIFS time first, then enter into sending state and do physical sense at the same time. We send data when channel is idle without waiting a random Back-off time. When CRC is encoding, The FIFO read mode is active to speed up the frame construction. The control frame of RTS-CTS-ACK is stored at the same block of the internal memory to avoid additional space used.
In the 802.11x standard, there are three kinds of frames which include control frame、data frame and management frame. These frames are implemented by software or hardware method. The MAC hardware handles the control and data frames, and the MAC software handles the management frame besides the beacon frame is constructed by hardware. The MAC hardware design is based on the DCF requirement function in MAC Layer, the DCF function works on the wireless LAN without AP association.
URI: http://hdl.handle.net/11455/7130
Appears in Collections:電機工程學系所

Show full item record
 

Google ScholarTM

Check


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.