Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/71323
標題: On-chip inductor above dummy metal patterns
作者: Hsu, H.M.
Hsieh, M.M.
關鍵字: chemical-mechanical planarization;dummy pattern;equivalent circuit;nanometer technology;on-chip inductor
Project: Solid-State Electronics
期刊/報告no:: Solid-State Electronics, Volume 52, Issue 7, Page(s) 998-1001.
摘要: 
This work characterizes the on-chip inductor above dummy metals in CMOS technology. Since the dummy pattern influences the sheet resistance in chemical-mechanical planarization ( CMP) process strongly [Schindler G, Steinlesberger G, Engelhardt M, Steinhogl W. Electrical characterization of copper interconnects with end-of-roadmap feature sizes. Solid-State Electron 2003;47:1233-36; Smith S, Walton A], Ross AWS, Bodammer GKH, Stevenson JTM. Evaluation of sheet resistance and electrical line width measurement techniques for copper damascene interconnect. IEEE Trans Semicond Manuf 2002;15:21422.], three test structures are fabricated to compare the inductor performances in this paper. The measurements show that the Q value degrades 15.3% and self-resonance frequency decreases 9.5% in device with dummy metal pattern. Accordingly, an equivalent circuit is proposed to analyze this behavior, the results show that the insulator capacitor plays a key role in performance degradation. Result of this study quantifies the effect of on-chip inductor above dummy pattern. (C) 2008 Elsevier Ltd. All rights reserved.
URI: http://hdl.handle.net/11455/71323
ISSN: 0038-1101
DOI: 10.1016/j.sse.2008.03.011
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