Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/71324
標題: Optimum bias of power transistor in 0.18 mu m CMOS technology for Bluetooth application
作者: Hsu, H.M.
Lee, T.H.
關鍵字: Bluetooth;CMOS technology;large-signal;optimum bias;power transistor;mosfet
Project: Solid-State Electronics
期刊/報告no:: Solid-State Electronics, Volume 50, Issue 3, Page(s) 412-415.
摘要: 
Based on the proposed silicon integrated power transistor adopting a 0.18 mu m technology, its performance shows this novel device can be operated at 2.4 GHz for Bluetooth and lithium battery applications [Hsu H-M, Su J-G, Chen C-W, Tang DD, Chen CH, Sun JY-C. Integrated power transistor in 0.18 pin CMOS technology for RF system-on-chip applications. IEEE Trans Microwave Theory Tech 2002;50(December):2873-81]. After executing matrix measurement of large-signal characteristics, the optimal quiescent point can be found, and the associated large-signal performance exhibits a maximum output power with 21.26 dBm, corresponding to a value of 44.3% for power added efficiency (PAE). Therefore, this device can be used in handholds for short-distance, low-power, and high-frequency operation. (c) 2006 Elsevier Ltd. All rights reserved.
URI: http://hdl.handle.net/11455/71324
ISSN: 0038-1101
DOI: 10.1016/j.sse.2006.01.016
Appears in Collections:期刊論文

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