Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/71324
DC FieldValueLanguage
dc.contributor.authorHsu, H.M.en_US
dc.contributor.authorLee, T.H.en_US
dc.date2006zh_TW
dc.date.accessioned2014-06-11T06:01:12Z-
dc.date.available2014-06-11T06:01:12Z-
dc.identifier.issn0038-1101zh_TW
dc.identifier.urihttp://hdl.handle.net/11455/71324-
dc.description.abstractBased on the proposed silicon integrated power transistor adopting a 0.18 mu m technology, its performance shows this novel device can be operated at 2.4 GHz for Bluetooth and lithium battery applications [Hsu H-M, Su J-G, Chen C-W, Tang DD, Chen CH, Sun JY-C. Integrated power transistor in 0.18 pin CMOS technology for RF system-on-chip applications. IEEE Trans Microwave Theory Tech 2002;50(December):2873-81]. After executing matrix measurement of large-signal characteristics, the optimal quiescent point can be found, and the associated large-signal performance exhibits a maximum output power with 21.26 dBm, corresponding to a value of 44.3% for power added efficiency (PAE). Therefore, this device can be used in handholds for short-distance, low-power, and high-frequency operation. (c) 2006 Elsevier Ltd. All rights reserved.en_US
dc.language.isoen_USzh_TW
dc.relationSolid-State Electronicsen_US
dc.relation.ispartofseriesSolid-State Electronics, Volume 50, Issue 3, Page(s) 412-415.en_US
dc.relation.urihttp://dx.doi.org/10.1016/j.sse.2006.01.016en_US
dc.subjectBluetoothen_US
dc.subjectCMOS technologyen_US
dc.subjectlarge-signalen_US
dc.subjectoptimum biasen_US
dc.subjectpower transistoren_US
dc.subjectmosfeten_US
dc.titleOptimum bias of power transistor in 0.18 mu m CMOS technology for Bluetooth applicationen_US
dc.typeJournal Articlezh_TW
dc.identifier.doi10.1016/j.sse.2006.01.016zh_TW
item.grantfulltextnone-
item.openairetypeJournal Article-
item.cerifentitytypePublications-
item.languageiso639-1en_US-
item.fulltextno fulltext-
item.openairecristypehttp://purl.org/coar/resource_type/c_18cf-
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