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標題: 應用於封包轉換器之高效能CAM在FPGA之實現
A High Utilization FPGA-based CAM for Packet Translation
作者: 蔡翔智
關鍵字: CAM;IPv6;IPv4
出版社: 電機工程學系
有鑑於今日網路上爆炸性的資料量,相較以往網路介面所需處理的資訊,我們必須要有更高速的解決方案。對終端路由器/交換器而言,其必須針對網路位址或是封包來做多區域性的搜尋,以此辨析所收到的封包所屬何方,因此,有多種針對封包分類的演算法被提出討論,但這些演算法對於硬體上的實現並不容易,於是在本篇論文中我們將針對以上所提的問題,並基於成本及實用上的考量,實現出一適用於IPv4/IPv6轉換器之改良型CAM。而在改良型CAM中,我們是利用前置處理器來判斷輸入資訊的種類,並以此來對輸入的資訊做有效分類,以期可達到將所收到的資訊快速且多區域性的分類,並以高密度的方式儲存ENTRY,此外我們也針對了優先權選擇器提出了以堆疊整合後利用Case方式的解決方案,以期讓系統達到高效率的運作。在我們的模擬結果中,改良型CAM的搜尋時間比起AR_CAM、ASIC CAM…等,大約可有36%以上的效能改進。

To deal with the exploding Internet traffic today, the network interfaces need to process more patterns than past, we must have more high-speed solutions. For terminal router / switch, it must aim at network addresses or packets to receive and search multi-fields and to distinguish where the received packets belong. Therefore, many packet classification algorithms had been discussed. However, these algorithms are not easy to be implemented in hardware. In this thesis, we will design an improved CAM which is suitable for IPv4/IPv6 switches. In this improved CAM, we used a pre-processor to do the classification of input patterns and classified them effectively. The input patterns with multi-field will be classified quickly, and the ENTRY will be saved with high density. Besides, for priority selector, we bring up a solution of using Case statement after stack and sort to let the system work with high efficiency. Finally, in our simulation results, receive and search time of the improved CAM has 36% efficiency improve meat than AR_CAM,ASIC CAM,etc.
Appears in Collections:電機工程學系所

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