低功率雙區間式類比數位轉換器之設計與實現

Abstract

This paper describes the design of an 8-bit low-power CMOS analog-to-digital converter with an improved subranging architecture. Only 15 comparators are used in this 8-bit ADC so that the chip area and power consumption is reduced. The dynamic latch-type comparators with zero static power consumption are used to implement the high-speed low-power A/D converter. The DAC uses an optimized multilevel tree decoding structure to reduce the settling time of the reference voltage of the A/D converter. The digital error correction technique is employed to ease component accuracy requirements and increase the resolution of the A/D converter. The subranging A/D converter is designed by use of a 0.5 μm UMC CMOS double-poly double-metal N-well process. Hspice simulation results show that the entire circuit only dissipates 19mW at 30MHz of sampling rate with a single 3.3 V power supply.

這篇論文主要描述一個採用改良式雙區間式架構的8位元、低功率、CMOS類比數 位轉換器之設計。這個8位元的類比數位轉換器只需使用15個比較器，因此減少了晶片面積 跟消耗功率。為了完成高速低功率的類比數位轉換器，我們使用了沒有靜態功率消耗的動 態栓鎖式比較器。在數位類比轉換器的部分，我們使用一個最佳化多重樹狀解碼結構來減 少類比數位轉換器的參考電壓的安定時間。數位錯誤更正技巧被用來減輕內部原件準確度 的要求及增加類比數位轉換器的解析度。此雙區間類比數位轉換器以0.5微米UMC CMOS double-poly double-meta1 N-well的製程設計。由Hspice的模擬結果顯示，整個電路在3.3V的電 源供應及30MHz的取樣頻率下，僅消耗19mW的功率。