Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/7232
標題: 可變繞線寬度電感與雙閘極金氧半場效電晶體之研究
Design of Variable Trace Width Inductor and Dual-Gate CMOS Transistor
作者: 詹凱淵
Chan, Kai-Yuen
關鍵字: inductor;電感;transistor;RF device;電晶體;射頻元件
出版社: 電機工程學系所
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Syrett, Member“A Comprehensive Design Method for Dual-Gate MOSFET Mixers” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 47, NO. 12, DECEMBER 2000 [14] Junghyun Kim, Student Member, IEEE, and Youngwoo Kwon, Member, IEEE “Intermodulation Analysis of Dual-Gate FET Mixers” IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 50, NO. 6, JUNE 2002 [15] Ryuichi Fujimoto, Member, IEEE, Kenji Kojima, and Shoji Otaka“A 7-GHz 1.8-dB NF CMOS Low-Noise Amplifier” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 7, JULY 2002 [16] Kung-Hao Liang, and Yi-Jen Chan“A 0.18 /spl mu/m dual-gate CMOS model for the design of 2.4 GHz low noise amplifier” Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 IEEE11-13 June 2006 Page(s) [17] Chen, Y.K.; Wang, G.W.; Radulescu, D.C.; Eastman, L.F.;“Comparisons of microwave performance between single-gate and dual-gate MODFETs” Electron Device Letters, IEEEVolume 9, Issue 2, Feb. 1988 Page(s):59 - 61 [18] Djelti, H.; Feham, M.; Kameche, M.; Ouslimani, A.;“On the advantages of GaAs dual-gate MESFET''s in comparison to Single-gate MESFET''s” Information and Communication Technologies, 2006. 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摘要: 
本論文分為兩部份,第一部份研究射頻積體電路中,可變繞線寬度電感最小金屬阻值演算法的佈局方式,這套演算法可以快速找出同面積及同電感值下的最佳繞線線寬設計,利用90nm CMOS製程實現我們所提出的電感,量測結果顯示可以改善了電感繞線電阻以及增加電感品質因素。分析同樣感值下,不同外徑、不同圈數及不同形狀電感對於自振頻率以品質因素之影響,而電感下方擺置Dummy Metal對於CMP製程中的片電阻影響十分嚴重,我們設計3顆電感元件,由量測結果及建立等效模型,分析Dummy Metal電感對於高頻特性損耗的原因。可變間距電感改良了可變寬度電感的設計,將間距效應加入設計考量,可變間距電感不但改善電感品質因素而且增加電感的自振頻率。
第二部份研究在疊接結構電路中,雙閘極電晶體與傳統單閘極電晶體之差異,量測結果顯示,雙閘極電晶體比單閘極電晶體有更好的高頻表現,藉由偏壓不同,分析雙閘極電晶體在截止頻率以及最大震盪頻率之表現,雙閘極電晶體將可以廣泛的應用在射頻積體電路中。

This thesis includes two parts. The first part studies on layout design algorithm of variable widths inductor to achieve minimum metal resistance. In this work, the proposed algorithm can rapidly find the optimal width by keeping identical inductance and chip area. The proposed inductors are fabricated by the foundry 90nm CMOS technology. Measurement results express that the variable width inductor improves the metal resistance and increases the quality factor of inductors. Furthermore, the variable width inductor includes the different outer dimension, turn numbers and geometry shape with identical inductances are compared in this work. Discuss the self-resonance frequency and quality factor effect in these inductors. Moreover, the investigation on dummy Metal pattern inserted under neath of on-chip inductor influences the performance. On the basis of measurement result, an equivalent model is proposed to analyze the phenomenon of Q value degradation in high frequency. Finally, an inductor with variable metal space between coils is proposed to improve the Q value. Variable space inductor not only improves the quality factor but also increases the self-resonant frequency.
The second part demonstrates that the cascode configuration of Dual-Gate MOSFET and compares the difference between conventional single gate MOS transistor. Keeping the identical bias condition, the high frequency performance of Dual Gate MOSFET is compared. Measurement results show that Dual Gate MOSFET has high cut-off frequency and excellent maximum oscillation frequency. Sweeping various bias conditions, the figure-of-merit of Dual Gate MOSFET is investigated deeply. Therefore, the Dual Gate FET can be widely applied in RF circuit design.
URI: http://hdl.handle.net/11455/7232
其他識別: U0005-0108200716125800
Appears in Collections:電機工程學系所

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