Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/7252
標題: 適用於JPEG2000之EBCOT記憶體架構分析以及高效能低成本電路實作設計
Memory Analysis and Throughput Enhancement for Cost Effective EBCOT Tier-1 Architecture in JPEG2000 Applications
作者: 邱肇民
Chiou, Tzau-min
關鍵字: JPEG2000
出版社: 電機工程學系
摘要: 
JPEG2000 Tier-1 coder is the most important technology in the latest still image compression standard , JPEG2000. According to the analysis for JPEG2000 ,JPEG2000 Tier-1 coder is the bottleneck of the system because the operations are bit-level processing and occupy more than half of the computation time of the whole compression process. A general purpose processor is ,therefore, very inefficient to process these operation.
In this thesis, a low cost and memory efficient bit-plane coder with throughput enhancement in JPEG2000 applications is proposed. Many literatures and the results of the chip implementation show that the memory requirements and the three coding passes dominate the hardware cost and the throughput rate of the EBOCT architecture respectively. In order to reduce the memory size, the memory-free algorithm is proposed to eliminate state variable memories by calculating three coding state variables (γp+1[n], σp+1[n], and πp[n]) on the fly. We also propose the stripe-column-based pass-parallel operation to perform three coding passes and four samples within the stripe-column concurrently. Moreover, the state variables are predictable as a result of our memory-free algorithm. Therefore, the proposed architecture is also a configurable architecture to exploit the parallelism of the bit-planes level to increase the throughput and to diminish the memory bandwidth. The experimental results show that the hardware cost and memory size of the proposed architecture is smaller than other existing architectures, and the proposed architecture has 3 times greater throughput than other familiar architectures.
URI: http://hdl.handle.net/11455/7252
Appears in Collections:電機工程學系所

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