Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/7260
標題: 應用於晶片間通訊的時脈資料回復電路及高效率介面電路之設計
A Clock/Data Recovery Circuit and an Efficient I/O for Chip-to-Chip Communication
作者: 李瑜
Lee, Yu
關鍵字: 高速序列傳輸;High-speed serial link;延遲鎖定迴路;鎖相迴路;時脈與資料回復電路;高效率介面電路;脈波寬度調變;脈波振幅調變;晶片間之通訊;Delay-Locked Loop;DLL;Phase-Locked Loop;PLL;Clock and data recovery;An efficient I/O circuit;Pulse-width-modulation (PWM);Pulse-amplitude-modulation (PAM);Chip-to-chip communication
出版社: 電機工程學系
摘要: 
近年來,隨著積體電路製程技術的進步以及處理器運算能力的與日遽增,使用於晶片和晶片間的串列傳輸技術也隨之蓬勃發展。因此本論文的研究將著重在設計高速序列傳輸系統之相關電路設計技術。文章內容主要分成四大部分。
首先,第一部分是探討一些傳輸的基本問題,例如通道建模和介面電路的雜訊來源。
第二部分則是探討鎖相迴路以及延遲鎖定迴路之設計。在此章節中將介紹鎖相迴路和延遲鎖定迴路的方塊圖,且會針對一些參數如頻寬、抖動效能及鎖定時間一一的做說明。另外,一些常用到的相位偵測器、電菏幫浦、壓控振盪器和壓控延遲線也將分類說明。
在第三部分,我們提出一個新式的相位檢測器運用在時脈與資料回復電路中。相較於傳統Hogge形式的相位檢測器,所提出的檢測器具有較低輸出抖動以及較寬相位捕獲範圍之特性。而此時脈與資料回復電路器是以0.35微米的互補式金氧半製程製造,晶片實際面積為750-um*900-um。當輸入資料率為1-Gb/s時,量測結果得到所回復之時脈均方根抖動及峰值抖動分別為17.94-ps以及120-ps;回復之資料均方根抖動及峰值抖動分別為29.88-ps以及170-ps。當電路鎖定時,晶片的消耗功率為64.8-mW而操作電壓為3.3-V。
最後,我們提出一個同時利用脈波寬度調變以及脈波振幅調變之高效率介面電路,相較於傳統的技術,此介面電路將可以在有頻寬限制之通道下傳送高速率的資料。所設計的符碼率為250-MHz,對應於1-Gb/s的資料速度,根據量測結果,傳送端之峰值抖動為160-ps,而回復所得的時脈在250-MHz下具有136-ps的峰值抖動,資料在250-Mb/s下具有150-ps的峰值抖動。傳送端所佔面積為867-um*996-um,接收端為1800-um*1800-um。傳送端以及接收端所消耗之功率分別為86-mW以及45-mW。

Recently, as the fabrication technology advances, combining with the increasing computational capability of processor, there is growing interest in the use of chip-to-chip serial links technology. The research of this thesis focuses on designing a high-speed serial link system. It is divided into four parts.
First, the first part of this text discusses some basic issues for the link, for example, channel modeling and signaling noise source.
The second part describes the design of the phase-locked loop (PLL) and the delay-locked loop (DLL). The building blocks of the PLL and the DLL are introduced, and the design issues of them include bandwidth requirement, jitter performance, and locked time are elucidated. Some commonly used circuits of the phase detector, the charge pump, the voltage-controlled oscillator and the voltage-controlled delay line are classified.
In the third part, a clock and data recovery (CDR) circuit using the new phase detector has been developed. Unlike the conventional Hogge's phase detector, the proposed detector has low output jitter and wide capture range characteristics. The CDR has been fabricated by 0.35-um N-well CMOS process and the active area occupies 750um*900um. When the input data rate is 1-Gb/s, the measured rms and peak-to-peak jitters for the recovered clock are 17.94-ps and 120-ps, respectively. And the measured rms and peak-to-peak jitters for the retimed data are 29.88-ps and 170-ps, respectively. The power consumption is 64.8-mW in the locked state at a 3.3-V supply voltage.
Finally, an efficient I/O employing the pulse-width-modulation (PWM) and pulse-amplitude-modulation (PAM) techniques is presented. In contrast with conventional techniques, it is implemented to effectively push high data rates through bandwidth-limited channels. The symbol rate is 250-MHz which corresponds to an equivalent data rate of 1-Gb/s. By experimental results, the measured peak-to-peak jitters for the transmitter output is 160-ps. And the recovered clock has a peak-to-peak jitters of 136-ps at 250-MHz, the retimed data has a peak-to-peak jitters of 150-ps at 250-Mb/s. The occupied die area is 867um*996um for the transmitter and 1800um*1800um for the receiver. The transmitter and receiver power consumption is 86-mW and 45-mW, respectively.
URI: http://hdl.handle.net/11455/7260
Appears in Collections:電機工程學系所

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