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Design of Dual-Path Low Density Parity Check Code Decoder
|關鍵字:||LDPC;錯誤更正碼;Low Density Parity Check Code;decoder;低密度同位元查核碼;解碼器||出版社:||電機工程學系所||引用:|| Simon Haykin, “Communication Systems 4th Edition,” John Wiley & Sons, Inc.  R. G. Gallager, “Low density parity check codes,” IRE Trans. Inf. Theory, vol. IT-8, no. 1, pp. 21-28,Jan.1962.  C. E. SHANNON, “A Mathematical Theory of Communication,” The Bell System Technical Journal, Vol. 27, July, October, 1948, pp. 379-426, 623-656.  Thomas J. Richardson and Rudiger L. Urbanke, “Efficient Encoding of Low-Density Parity-Check Codes,” IEEE Transactions on Information Theory Vol. 47, NO.2, Feb 2001 pp.638 - 656  Xiao-Yu Hu, Evangelos Eleftheriou, Dieter-Michael Arnold, and Ajay Dholakia, “Efficient Implementations of the Sum-Product Algorithm for Decoding LDPC Codes,” IEEE Global Telecommunications Conference, pp.1036-1036E, 2001  Artisan Standard Library Register File Generator User Manual  Shu Lin, J. Daniel, Jr. Costello, “Error Control Coding Fundamentals and Applications,” New Jersey, NJ: Prentice-Hall, 1983.  Sang-Min Kim and Keshab K. Parhi, “Overlapped decoding for a class of quasi-cyclic LDPC codes,” IEEE Signal Processing Systems, 2004. SIPS 2004. pp.113-117  A. Blanksby and C. Howland,“A690-mw1-Gb/s 1024-b,rate-1/2 low-density parity-check code decoder,” IEEE J. Solid-State Circuits, vol. 37, no. 3, Mar.2002, pp.404-412  Chien-Ching Lin, Kai-Li Lin, Hsie-Chia Chang and Chen-Yi Lee, “A 3.33Gb/s(1200,720) Low-Density Parity Check Code Decoder,” Solid-State Circuits Conference, 2005. Proceedings of the 31st European pp. 211-214  Sang-Min Kim; Parhi, K.K., “Overlapped decoding for a class of quasi-cyclic LDPC codes,” IEEE Signal Processing Systems, 2004., pp. 113-117.  Hao Zhong and Tong Zhang, “Design of VLSI Implementation-Oriented LDPC Codes,” IEEE Semiannual Vehicular Technology Conference (VTC), Oct. 2003, pp.670~673  Jeremy Thorpe, “Design of LDPC Graphs for Hardware Implementation,” 2002 IEEE International Symposium, Information Theory, pp483  Emmanuel Boutillon, Jeff Castura, Frank R.Kschischang, “Decoder-First Code Design,” in Proceeding of the 2nd International Symposium on Turbo code and Related Topics, Brest, France, September 2000, pp. 459~462  Joachim Hagenauer, Fellow, ZEEE, Elke Offer, and Lutz Papke, “Iterative Decoding of Binary Block and Convolutional Codes,” IEEE Transactions on Information Theory, Vol. 42, NO. 2, March 1996 pp. 429-445||摘要:||
本論文提出了一個高傳輸速度的低密度同位查核碼解碼器之硬體設計電路，使用矩陣大小為500×1500、行權重及列權重分別為3、9之規則隨機查核矩陣，在硬體架構上分成四個單元，分別為：變數點單元、查核點單元、記憶體單元及配置單元。記憶單元利用了Artisan 2-Ports Register File架構而成，並經由適當的規劃大幅降低了Register File所需要的個數及面積；查核點單元以min-sum演算法來做為硬體設計原則。
本論文之設計以TSMC 0.18μm CMOS技術合成，在頻率為166MHz、解碼次數為8次時，傳輸速度可達到3.79Gbps，cell area為9.78 M (μm2)，功率消耗為2204 mW。
In this thesis, a high throughput decoder for Low Density Parity Check Code is presented. The (500, 1500) check matrix is a random and regular matrix whose column weight and row weight are 3 and 9, respectively. The design includes 4 units, which are Variable Node Unit (VNU), Check Node Unit (CNU), Memory Unit and Distributor. The Memory Unit is composed of Artisan 2-Ports Register File. The size of the Register File was reduced greatly by appropriate arrangement. The Min-sum algorithm was applied in CNU.
During the decoding process, CNU and VNU operations are active alternatively in every decoding iteration. To increase the throughput, these idled CNU or VNU circuit blocks can be used to process another codeword, thus, the throughout is increased to almost two times. Moreover, if pipelined architectures are applied to both VNU and CNU, the clock rate cnn be increased, which makes 2.5 times the throughput of the original one.
In this thesis, the design was synthesized using TSMC 0.18 μm CMOS technology. It can achieve 3.79 Gbps throughput with 8 iterations in 9.78 M(μm2) cell area. The power dissipation is 2204 mW at clock frequency of 166MHz..
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