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標題: 用基底2⁴SDF架構實現有效率及低乘法器花費的256點快速傅利葉轉換設計
Efficient Low Multiplier Cost 256-Point FFT Design with Radix-2⁴ SDF Architecture
作者: 范志鵬
關鍵字: 快速傅利葉轉換;SDF;單路徑延遲回授結構;數位信號處理;Fast fourier transform;FFT;Single-path delay feedback structure;SDF structure;Digital signal processing
出版社: 國立中興大學工學院;Airiti Press Inc.
Project: 興大工程學刊, Volume 19, Issue 2, Page(s) 61-74.
In this paper, we propose an efficient and low-cost 256-point fast Fourier transform (FFT) architecture and implementation, especially for WiMAX OFDM system. Based on the radix-16 FFT algorithm, the proposed 256-point FFT processor utilizes simplified cascaded radix-2? single-path delay feedback (SDF) structure. The control circuit of the proposed simplified radix-2? FFT SDF architecture is simpler than that of the direct radix-16 FFT SDF structure. The multiplier cost of the proposed FFT architecture is less than that of the previous FFT structures in 256-point FFT applications. The throughput of the proposed FFF processor is one sample per clock. In hardware verifications, the throughput of our FFT design processes up to 35.5 M samples/sec with Xillinx Virtex2 1500 FPGA, and it processes up to 51.5 samples/sec with UMC 0.18 μm standard cell technology. The throughput of our FFT is suitable for WiMAX 802.16a application, whose maximum sample rate is 32 MHz.

在本論文中,我們提出一可用於WiMAX OFDM通訊系統的有效率及低乘法器花費的256點快速傅利葉轉換(FFT)架構及其實作。利用基底16快速傅利葉轉換演算法,本論文所提出的256點快速傅利葉轉換處理器使用簡化的串接基底2?單路徑延遲回授(SDF)結構。此提出的簡化型的基底2?單路徑延遲回授架構的控制電路,比直接基底16快速傅利葉轉換單路徑延遲回授(SDF)結構來得簡單。本論文所提出快速傅利葉轉換架構乘法器花費少許之前的256點快速傅利葉轉換架構。本論文提出的快速傅利葉轉換處理器的產出率為每一時脈週期輸出一筆取樣資料。使用Xilinx Virtex2 1500 FPGA硬體實作可知,我們所提出快速傅利葉轉換設計的產出率最快可達到每秒輸出35.5百萬筆資料。若使用UMC 0.18 ?m標準細胞電路庫硬體實作可知,我們所提出快速傅利葉轉換設計的產出率最快可達到每秒輸出51.5百萬筆資料,因此本論文所提出快速傅利葉轉換設計的產出率可適用於32MHz的WiMAX 802.16a的應用。
ISSN: 1017-4397
Appears in Collections:第19卷 第2期

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