Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/7276
標題: 可重組化數位訊號處理核心電路架構於多媒體應用之設計與實現
Design and Implementation of a SIMD-based Reconfigurable DSP Core for Multimedia Applications
作者: 楊宗錕
Yang, Tzong-Kun
關鍵字: Reconfigurable;可重組化計算;vector;ALU
出版社: 電機工程學系
摘要: 
由於晶片製作的技術一再進步,傳統的特殊用途晶片已經不能再符合我們的要求,可重組化的特性就是能適用於不同的運用在同一套的硬體上,對於不同的應用如多媒體或是訊號處理(DSP)上面的特殊且複雜的演算法都能夠快速而且容易的在我們的可重組化的硬體上實現,我們可以藉由可重組化的連接網路和處理單元能做不同高資料平行度而且又計算複雜的演算法,這樣不但能降低我們設計的成本, 也能達到高效能的目的,對於傳統的一般用途的處理器, 由於我們有高效能可重組化網路的連接,我們就能去面對不同的規則性但是運算量高的演算法,例如移動估計演算法,離散餘弦轉換等, 這些演算法在多媒體裡面都是高運算量但是有高規則性的運算。
我們的架構裡面有著2個向量化的運算單元1個資料以及指令的記憶體,我們提出的是適用於數位訊號處理的動態混合顆粒可重組化計算架構,可實現多個Byte階層的計算和特殊的乘法單元,向量化的算數邏輯運算單元中整合一個連線單元提供運算元有效率的使用,最後我們也實現一些多媒體及數位訊號處理方面的運用,離散餘弦轉換以及矩陣乘法在我們的架構上實現來分析它的效能,由於這個我們提出的可重組化架構我們便可以不再使硬體只有單一特殊應用,也能夠依照不同的運用以改變硬體,能節省晶片發展成本。

As VLSI technology continues to improve, reconfigurable computing has opened new frontiers in the field of computer architecture. The disadvantage of AISC, less flexible and high cost, is inefficient to use. Our purpose, reconfigurable architecture, can achieve both high performance of ASIC and the flexibility. Because reconfigurable hardware can map on different application, we re-use it only by re-configured. It is obvious to reduce design cost instead of ASIC, needed re-designed a new chip for different application. And reconfigurable hardware contained flexible function units and re-configured interconnect network. According to above, our purpose has more flexible than general purposed processor. In recently, there are many new reconfigurable architectures are investigated. This work proposed a new model of reconfigurable computing architecture. We developed to investigate the effectiveness of combining multiple reconfigurable function units for word level.
Our purpose is a coarse-grain, integrated reconfigurable system-on-chip targeted at high throughput and data-parallel application such as video compression. It comprises 2 SIMD-based Reconfigurable Vector ALU, 2 instruction memories, 2 data memories. In each ALU, it supports 5 stage pipeline and special instruction for matrix computation, complex number computation, DOT, and butterfly algorithm. Vector ALU can perform different word level, ex. 8-, 16-, 32- bits, arithmetic operation and 8-, 16- 32-bits multiplication. Cross_box provide flexibility of operand for load/store data and data allocation. Therefore, the reconfigurable DSP core can perform a lot of operations flexibly. It was in its infancy. We will enhancements on the system adaptability for different classes of applications in further.
URI: http://hdl.handle.net/11455/7276
Appears in Collections:電機工程學系所

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