Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/7283
標題: 改良式二相位和四相位電荷幫浦及電壓調節器設計
Design of modified two-phase and four-phase charge pumps with voltage regulator
作者: 李俊欣
Li, Jin-Shin
關鍵字: charge pump;幫浦;voltage regulator;boost;電壓調節器;高電壓
出版社: 電機工程學系所
引用: [1] 鐘淑婷,“高電壓直流調節器之電路設計,”2006年碩士論文,國立中興大學 [2] 王寵智,“低供應電壓之高電壓整流器電路設計,”2005年碩士論文, 國立中興大學 [3] Umezawa A., Atsumi S., Kuryiama M., Banba H., Imamiya K., Naruke K., Yamada S., Obi E., Oshikiri M., Suzuki T. and Tanka S. “A 5V only operation 0.6μm Flash EEPROM with row decoder scheme in the triple well structure,” IEEE J. Solid-State-Circuits, vol. 27, pp. 1540-1546, Nov 1992. [4] J.Dickson,“On-chip high-voltage generation NMOS integrated circuits using an improved voltage multiplier technique,” IEEE J. Solid-State Circuits, vol. SC-11, pp. 374-378, Mar. 1976. [5] Jieh-Tsorng Wu and Kuen-Long Chang, ”Low supply voltage CMOS charge pumps,“ Symposium on VLSI Circuits Digest of Technical Papers, pp. 81-82, June 1997. [6] Jieh-Tsorng Wu, Kuen-Long Chang, ”MOS charge pumps for low-voltage operation,” IEEE J. of Solid-State Circuits, vol. 33,no. 4, pp. 592-597, April 1998. [7] Kyeong-Sik Min and Jin-Hong Ahn, ”MOS charge pumps using cross-coupled charge transfer switches with improved voltage pumping gain and low gate-oxide stress for low-voltage memory circuits,” IEICE Trans Electron, vol. e85-c, no. 1, pp. 225-229, January 2002. [8] P. Favrat, P. Deval, and M. J. Declercq, “A high-efficiency CMOS voltage doubler,” IEEE J. Solid-State Circuits, vol. 33, pp. 410-416, March. 1998., [9] M. Ker, S. Chen, and C. Tasi, “Design of charge pump with consideration of gate-oxide reliability in low-voltage CMOS processes,” IEEE J. Solid-State Circuits, vol. 44, pp. 1100-1107, May. 2006. [10] Jongshin Shin, In-Young Chung, Young June Park, and Hong Shick Min, “A New Charge Pump Without Degradation in Threshold Voltage Due to Body Effect,” IEEE J. Solid-State Circuits, vol. 35, No. 8, pp. 1227–1230, Aug. 2000. [11] P. E. Allen, B. J. Blalock, and G. A. Rincon, “A 1-V CMOS opamp using bulk-driven MOSFETs,” in IEEE ISSCC Dig. Tech. Papers, pp. 192–193, 19950. [12] Christl Lauterbach, Werner Weber, and Dirk Romer, “Charge Sharing Concept and New Clocking Scheme for Power Efficiency and Electromagnetic Emission Improvement of Boosted Charge Pumps,” IEEE J. Solid-State Circuits, vol. 35, no. 5, pp. 719–723, May 2000. [13] Ming-Dou Ker,Shih-Lun Chen and Chia-Sheng Tsai,“A New Charge Pump Circuit Dealing With Gate-Oxide Reliability Issue In Low-Voltage Processes,” Int. Sym. Circuits and Systems, vol. 1, pp. 321–324, May 2004. [14] Joseph S. Shor, Yan Polansky, Yair Sofer ,and Eduardo Maayan, “Self-regulated Four-Fhased Charge Pump with Boosted Well,” Int. Symp. Circuits and Systems, vol. 1, pp. 241–244, May 2003. [15] Jae-Youl Lee, Sung-Eun Kim, Seong-Jun Song, Jin-Kyung Kim, Sunyoung Kim, and Hoi-Jun Yoo. “A regulated charge pump with small ripple voltage and fast start-up,” IEEE J. Solid-State Circuit, vol. 41, pp. 425–432, Feb 2006. [16] J. Soldera, A. Vilas Boas, and A. Olmos, “A Low Ripple Fully Integrated Charge Pump Regulator,” IEEE Symp. Integrated Circuits and System Design, pp. 177–180, Sept 2003. [17] Hongchin Lin and Nai-Hsien Chen, “New Four-phase Generation Circuits for Low-voltage Charge Pumps,” IEEE Int. Symp. VLSI Technology, Systems & Application, pp. 228-231, 2001. [18] Philip E. Allen and Douglas R. Holberg, CMOS Analog Circuit Design, 2nd ed. New York, NY: Oxford, 2002. [19] David A. Johns and Ken Martin, Analog Integrated Circuit Design, Canada: Wiley, 1996.
摘要: 
本論文內容主要介紹應用於非揮發記憶體的低供應電壓之高電壓整流器電路。本論文的研究重點有二:其一為改良電荷幫浦電路,並比較各種方法的優缺點;另ㄧ重點為低漣波電壓調節器之電路設計。
在0.35μm CMOS製程技術中,由於是雙井製程,因此可用之電荷幫浦電路較有限制,因此選擇了兩種,其一是雙重式四相位正電荷幫浦電路,另一為適用於雙/三井製程之二相位電荷幫浦電路。而0.18μm CMOS製程技術,由於是三井製程,因此電荷幫浦變化較多,本論文選擇了一種四相位與三種改良式二相位來比較。其中以適用於雙/三井製程之二相位電荷幫浦電路及可產生正負電壓之二相位電荷幫浦的輸出電壓及效率較佳。其中後者當使用4級與供應電壓為1.8伏特時,可以產生高達8.65或-6.8伏特的輸出電壓。
最後,選擇磁滯比較器來控制電荷幫浦電路輸出結果,主要優點為改善電荷幫浦電路的輸出漣波電壓及避免受到雜訊的影響,而運用磁滯比較器之電壓調節器架構的其漣波較小及較省電。現階段已經將4級電荷幫浦電路加上電壓調節器的輸出被限制在7V時,輸出漣波電位降至240mV以下,且可承受負載電流為1.6mA。

The thesis is to present a high DC to DC voltage regulator circuit at low supply voltage for non-volatile memories. The thesis is focused on two topics. The first topic is to improve the charge-pumping circuits and do the comparison with the other pumping circuits. The second one is to design low ripple voltage regulator circuits.
The charge pumping circuits are limited if the twin-well process, such as 0.35 μm CMOS technology is used. Here, two charge pumping circuits are investigated. The first one is a dual four phase positive charge-pumping circuit .The other is the two-phase charge-pumping circuit for the twin or triple well process. For the triple well process like 0.18μm CMOS technology, more different pumping circuits can be applied. This thesis investigates one four-phase and three modified two-phase pumping circuits and compare their performance. The boosted voltage and power efficiency of the two-phase charge pump using twin-well process and the positive/negative charge pump are better than those of the other. The simulation results show the boosted voltage could reach 8.6V and -6.8V at supply voltage 1.8V using the 4-stage positive/ negative charge pump.
Finally, a hysteresis comparator is utilized to regulate the output voltage of charge pumping circuit for the smaller output ripple and less influence by the noise as well as less power consumption. The voltage regulator using four-stage charge pumping circuits generates a constant 7V with the output ripple less than 240mV and the loading current of 1.6mA
URI: http://hdl.handle.net/11455/7283
其他識別: U0005-0208200714035300
Appears in Collections:電機工程學系所

Show full item record
 

Google ScholarTM

Check


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.