Please use this identifier to cite or link to this item:
標題: 嵌入式EEPROM之電路與系統設計
Circuits and Systems Design for Embedded EEPROM
作者: 林映助
Lin, Ying-Chu
關鍵字: 嵌入式記憶體;embedded EEPROM:VCO;振盪器
出版社: 電機工程學系所
引用: 參考文獻 [1] B. Razavi,李峻霣譯, ”類比CMOS積體電路設計,”滄海書局,中華民國九十三年一月. [2] N. H. E. Weste, K. Eshraghian,黃淑娟譯, ”CMOS VLSI設計原理,” 偉明圖書有限公司,中華民國九十一年十一月. [3] 沈祐民, ” Multilevel Sensing ang Verifying Circuit for Flash Memory,” 2004年碩士論文,中興大學. [4] 李昆鴻,”Study of High-Qensity Embedded Single-Polysilicon Nonvolatile Memory ,” 2005年博士論文,清華大學. [5] 鍾秋嬌,” Bi-level and Multi-level Sensing/Verifying Related Circuit Design for Non-Volatile Memories,” 2007年博士論文,中興大學. [6] K. Itoh, ”VLSI Memory chip Design,”Springer,Jan., 2001 [7] M. M. Mano, ” Digital Design,” Prentice Hall, Aug., 2001. [8] H.-F. A. Chou, et al., “Comprehensive study on a novel bi-directional tunneling program/erase NOR-type (Bi-NOR) 3-D flash memory cell,” IEEE Trans. Electron Devices, vol. 48, pp. 1386-1393, 2001. [9] C. –S. E. Yang, et al., “New buried bit-line NAND (Bi-NAND) Flash memory for data storage,” Symp. VLSI Tech. Dig., pp. 95-96, 2003. [10] A. Chrisanthopoulos, Y. Moisiadis, A. Varagis, Y. Tsiatouhas, and A. Arapoyanni, “A new Flash memory sense amplifier in 0.18 μm CMOS technology,” Proc. IEEE Int. Conf. Electronics, circuits, and Systems (ICECS), vol. 2, pp. 941-944, Sep., 2001. [11] J. F. Dickson, “On-chip high-voltage generation in NMOS integrated circuits using an improved voltage multiplier technique,” IEEE J. Solid-State Circuits, vol. sc-11, pp. 374-378,Jun., 1976. [12] Hong-chin Lin and Nai-Hsien Chen, “An Efficient Clock Scheme for Low-voltage Four-phase Charge Pumps,” IEEE Int. Symp. Circuits and Systems, vol. 1, pp. 504-507, 2001. [13] D. Hilbiber “A new Semiconductor voltage standard,” in ISSCC Dig. Tech. Papers, pp. 32-33, Feb. 1964. [14] K. E. Kujik. “A Precision Reference Voltage Source” IEEE J. Solid-State Circuits, vol. 8, pp. 222-226, Jun., 1973. [15] Kung-Hong Lee and Ya-Chin King, “New single-poly EEPROM with cell size down to 8F/sup 2/ for high density embedded nonvolatile memory applications,” VLSI Technology Symposium, Kyoto, Japan, pp. 93-94, 2003. [16] Kung-HongLee,Shih-Chen Wang, Ya-Chin King, “Self-convergent scheme for logic-process-based multilevel/analog memory,” Electron Devices, IEEE Transactions, pp. 2676 – 2681, Dec. 2005. [17] Kung-Hong Lee, Shih-Chen Wang, Ya-Chin King, “Novel self-convergent scheme logic-process-based multilevel/analog EEPROM memory,” Memory Technology , IEEE International Workshop , pp. 3-8, Aug. 2005 [18] R. Micheloni, L. Crippa, M. Sangalli, and G. Campardo, “The Flash Memory Read Path: Build Blocks and Critical Aspects,” proceedings of IEEE, pp. 537-553, Apr., 2003. [19] Chiu-Chiao Chung, Hong-chin Lin,Yen-Tai Lin, “A Novel High-Speed Sense Amplifier for Bi-NOR Flash Memories,” IEEE J. solid-state circuits, vol. 2,Feb., 2005. [20] R.chebli, X.Zhao and M. Sawan, “A Wide Tuning Range Voltage-Controlled Ring Oscillator dedicated to Ultrasound Transmitter,”The 16th international conference on , pp.313-316, dec., 2004. [21] Chiu-Chiao Chung, Hong-chin Lin,You-Min Shen and Yen-Tai Lin, “A Multilevel Sensing and Program verifying scheme for Bi-NAND Flash Memories,” IEEE VLSI-TSA International Symposium, pp. 267-270, apr., 2005. [22] G. Campardo, R. Micheloni, D. Novosel, ”VLSI-Design of Non-Volatile Memories,”Springer,Oct., 2004.
近年來,因應多媒體設備的需求,我們不斷地在密度、功率、以及生產量上提高記憶體元件的效能。各式記憶體元件與其相關週邊電路均朝向快速、低成本且高密度操作的設計趨勢。而這次我們研究的主要記憶體元件是利用標準0.35μm CMOS製程的Single-poly EEPROM記憶體結構來達到高密度、低成本以便應用於系統晶片(SOC)。
本論文是設計上述之記憶體之週邊相關電路,主要目標是設計嵌入式EEPROM系統由概念到實現的完整流程,而整個電路系統包含了記憶體陣列,位址解碼電路,電壓選擇與驅動電路以及時脈控制電路,功能選擇方面則有寫入、抹除及單純讀出三種,單一次寫入或抹除時間為1ms而讀出的時間為100ns且寫入、抹除及讀出會重覆數次直到成功才停止,因此設計了一組電壓控制震盪電路來控制寫入及抹除的時間,讀出的時間則由另ㄧ組電壓控制延遲電路來做控制,功率的消耗為寫入時13.01mW,抹除時12.44mW,並使用TSMC 0.35μm CMOS 2P4M製程模擬並且下線,晶片面積是1.4*1.4mm 2。

In recent years, because of in conformity with the demand for the multimedia equipment, the efficiency of the storing device components have great improvements on chip density, power and mass production continuously. Various types of data storge devices and their related periphery circuit are designed for fast, low cost and high density. The major topic that we investigate in this thesis is non-volatile memory circuits usung the standard 0.35μm CMOS Single-poly technology for high density, low cost and applications to SOC.

This thesis is a design of related periphery circuits of the aforesaid storage device, The main goal is to design embedded EEPROM systems from the concept to realize. The complete circuits and systems include the cell array of EEPROM, address decoder, voltage selection and voltage driver circuits and control signal generator. There are three required functions, including program, erase and read. The time for program or erase is 1ms and the time of read is 100ns. The control signal generator will repeat the same process several times if the data are not programmed or erased to the targets. Therefore we designed a voltage control oscillator circuit to control the time of program or erase. We also designed a voltage controled delay time circuit to control the time of read. The power consumptions are 13.01mW during the time of program and 12.44mW during the time of erase. The whole circuits and systems have been simulated and fabricated using TSMC 0.35μm CMOS 2P4M technology in area of 1.4*1.4mm 2 .
其他識別: U0005-0208200714233600
Appears in Collections:電機工程學系所

Show full item record

Google ScholarTM


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.