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Lossless Data Compression for Multi-Dimension Images and Its Embedded System Implementation
|關鍵字:||lossless compression;無失真壓縮;adaptive filter;Multi-Dimension Images;Embedded System;HW/SW codesign;適應性濾波器;多維度影像;嵌入式系統;軟硬體共設計||出版社:||電機工程學系所||引用:|| MRI Images, [Online]. Available: http://www.slicer.org/  J. R. Fogler, “Multi- and Hyper-Spectral Sensing for Autonomous Ground Vehicle Navigation”, Sandia National Labs, Sandia Report SAND, 2003. pp 25-29.  AVIRIS Images in CCSDS test set, Jet Propulsion Laboratory, NASA. [Online]. Available: http://compression.jpl.nasa.gov/hyperspectral  “JPEG-LS; Lossless and near-lossless coding of continuous tone still image,” ISO/IEC JTC 1/SC 29/WG 1 FCD 14495, July 1997.  M. J. Weinberger, G. Seroussi, G. Sapiro, “The LOCO-I lossless image compression algorithm : principles and standardization into JPEG-LS”, IEEE Trans. Image Process., 2000, 9, pp. 1309-1324  N. Memon and X. Wu, “Context-based adaptive, lossless image coding,” IEEE Trans. Commun., vol. 45, no. 4, pp. 437-444, Apr. 1997.  X. Wu and K. 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E89-D, no. 7, pp. 2250-2256, July 2006.  “Arithmetic Coding”, Ch. 7, Fundamentals of Multimedia , edited by Z. N Li, M.S Drew, 2004, Pearson Education International.||摘要:||
本論文提出一個有效多維度影像無失真壓縮系統。目標在於不改變內容前提下減少資料傳送的頻寬與儲存空間，應用包括醫學影像、衛星影像、數位影像的保存諸如此類。目前標準無失真壓縮演算法如JPEG-LS、JPEG 2000、 CALIC以及I-CALIC，其壓縮效率仍不能滿足需求。我們提出的系統分為三個部分，包含前處理、預測和編碼。首先，前處理主要分析輸入影像特性如影像成影特性以及資料相關性。依據資料型態，預測能夠實現於時間、空間、頻譜和體積域 (4-D)。預測技術包含最小平方(Least Square)、Weiner filtering與線性/非線性預測。而在某些領域呈現突出的資料相關性，並且有助於預測在這些領域利用更多的資料相關性獲得更好預測效率，例如多頻帶影像的頻譜域和視訊資料的時間域。預測能夠更進一步搭配資料轉換以提高性能。對於此組合方案，一個動態補償時間濾波器（MCTF）搭配小波轉換結合已經被提出。編碼技術包含前文參考之適應性算術編碼(CBAAC) 和前文參考之 Golomb-Rice 編碼(CBGRC) 壓縮技術。基於這個架構，針對不同型態的影像發展出對應的無失真壓縮系統，包括第三章節到第五章節所描述之視訊、醫學影像和多頻帶影像無失真壓縮系統。
這些系統經由實驗驗證，都呈現非常良好之壓縮效率。對於視訊影像，借助適應性MCTF和空間預測幫助，該系統可以獲得 2至4倍壓縮率。對於單一或4-D醫學影像資料，結合適應性最小平方預測、適應性誤差反饋和上下文編碼的壓縮系統，可達成4到8倍的壓縮率。多頻帶影像在頻譜域中呈現出強烈資料相關性，採用兩階段預測與一階熵編碼技術的壓縮系統最佳可獲致4倍的壓縮率。相較於現有先進壓縮演算法如JPEG-LS、JPEG2000 與 I-CALIC，本論文所提出之各類壓縮系統皆有較佳之表現。
除了演算法開發之外，本論文中也探討系統實現問題。根據第五章節所提出多頻帶影像壓縮系統，第六章中探討採用ARM+FPGA嵌入式平台上的系統實現。依據軟硬體共設計原理，將運算需求較高的模組(如預測模組)以硬體加速器實現在FPGA，其餘部分以軟體方式實現。除此之外，並套用了各種軟硬體設計最佳化技術。最後系統實現的處理速度，相較於單純軟體系統，可提升21倍之多。使用TSMC 0.18um 1P6M CMOS技術，也完成了硬體加速器的晶片設計。當運作40MHz條件下，最大資料處理速率為每秒16.5Mpixel。晶片設計大小為5.38 mm2，而量測功率消耗為169 mW@ 40MHz。
In this dissertation, a lossless data compression system for multi-dimension images is proposed. Lossless compression is essential to those applications where information loss during the compression process is not acceptable; and multi-dimension images are those with volumetric data in 3 or even higher dimensions. Our goal is to achieve high compression efficiency to alleviate the massive data storage and communication bandwidth problems. Target applications include digital image/video archiving, medical images for diagnosis, and hyperspectral images for satellite remote sensing.
Current lossless compression tools such as JPEG-LS, JPEG 2000, CALIC and CALIC fail to provide satisfactory compression rate, which confines their applications mostly to 2-D images only. In the dissertation, the proposed lossless compression system consists of 3 processing modules, i.e., pre-processing, prediction, and residual coding. The pre-processing module assumes the role of image analysis, which includes extracting the image features and the data correlation. Depending on the data types, the prediction is performed along the temporal, spatial, spectral and even volumetric (4-D) domains. The employed prediction schemes include least square, Weiner filtering, and linear/non-linear predictions. Although more prominent data correlation may appear in certain domains, e.g. the spectral domain in hyperspectral images and the time domain in video data, supplementary prediction applied to the remaining domains helps exploit more data correlation for better prediction efficiency. The prediction can be further coupled with data transforms to enhance the performance. For such composite schemes, a combination of motion compensated temporal filtering (MCTF) and wavelet transform is proposed. In residual coding, techniques employed include Context-based adaptive arithmetic coding (CBAAC) and Context-based Golomb-Rice coding (CBGRC). Based on this framework, various lossless compression systems have been developed subject to different types of image data. The systems presented in chapter 3 to chapter 5 are tailored to video, medical images and hyperspectral images, respectively.
Experiments on these systems have been conducted to demonstrate the compression efficiency and the results are very promising. For video source, with the help of an adaptive MCTF scheme and supplementary spatial predictions, the proposed system can yield a compression ratio ranges from 2 to 4. For single or volumetric medical image data, a combination of adaptive least square prediction, adaptive error feedback and context based coding leads to an efficient prediction scheme achieving a pronounced compression ratio ranging from 4 to 8. For hyperspectral images, which exhibit strong data correlation along the spectrum, a two-stage prediction scheme followed by a first order entropy coder gives rise to a significant compression ratio up to 4. Comparisons with existing state-of-the-art compression algorithms such as JPEG-LS, JPEG2000, and I-CALIC are also performed and the performance edges of the proposed systems are undoubtedly verified.
Besides the algorithm developments, the system implementation issues are also investigated in this dissertation. Based on the hyperspectral image compression scheme presented in chapter 5, an efficient embedded system implementation on an ARM + FPGA prototyping platform is presented in chapter 6. Following the principle of HW/SW codesign, the system employs a dedicated hardware accelerator realized in an FPGA to implement the most computation intensive module, i.e., the prediction module, of the compression system. The remaining of the system is coded in software for the flexibility. With the application of various optimizing techniques, the system shows a 21 times speed up compared to a purely software implementation. The hardware accelerator design is further fabricated to a chip using TSMC 0.18um 1P6M CMOS technology. The maximum throughput is as high as 16.5Mpixel/sec when working at 40MHz. The core size of the chip design is 5.38 mm2 and the measured power consumption at 40MHz is only 169 mW.
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