Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/7325
標題: JPEG 2000之記憶體精簡方塊編碼器電路架構設計與實現
VLSI Architecture Design and Implementation of the Memory Efficient Block Coding Engine for JPEG 2000
作者: 黃泰綸
Huang, Tai-Lun
關鍵字: EBCOT;方塊編碼;block coding;JPEG 2000;pass-parallel;影像壓縮
出版社: 電機工程學系
摘要: 
在最新的靜態影像壓縮標準JPEG 2000中,具最佳中斷點的嵌入式方塊編碼演算法(EBCOT)是一項很重要的技術。根據分析,JPEG 2000的運算複雜度有超過一半都落在EBCOT的方塊編碼部份,其主要原因在於方塊編碼運算為位元級的,並不適合在一般用途的處理器上做運算,因此方塊編碼器的硬體設計就顯得格外重要。
在本篇論文中,提出了一個新的高度平行且節省記憶體的EBCOT架構,藉由所提出的(1)記憶體節省演算法,數值增量(MR)狀態變數記憶體可被重要性(Significance)狀態變數記憶體的邏輯運算所取代。以這演算法為基礎,我們的EBCOT架構不僅可以同時對兩個位元平面做編碼,還免除了MR狀態變數記憶體的使用;此外,再配合所提出的(2)以行為基礎的平行運算方式,讓位元平面編碼的三個步驟合併為一個步驟來執行,以增進我們系統整體的運算效能。綜合以上的的方法,根據實驗結果顯示,本論文所提出的架構和以前的加速方法相比,可以減少超過 80% 的運算時間。
最後,我們以 UMC 0.18um 1P6M 的製程完成了方塊編碼器的雛形晶片設計,晶片面積為 1210 x 620 (um)。模擬結果顯示晶片的最高操作頻率為 100 MHz,平均功率消耗為 78.4 mW。

Embedded block coding with optimized truncation (EBCOT) is the most important technology in the latest still image compression standard, JPEG 2000. The hardware design of the block-coding engine in EBCOT is critical because the operations are bit-level processing and occupy more than half of the computation time of the whole compression process. A general purpose processor is, therefore, very inefficient to process these operations.
In this thesis, a novel highly parallel and memory efficient EBCOT architecture for JPEG2000 applications is proposed. By the proposed (1) memory saving algorithm, the memory modules for the magnitude refinement (MR) state variable can be eliminated by the significance state variable. Based on the proposed memory saving algorithm, our EBCOT architecture not only simultaneously perform the three-pass coding algorithm for two adjacent bit-planes but also save the MR state variable memory to achieve memory efficient requirements. Moreover, the three-pass coding algorithms are also performed in parallel by the proposed (2) column-based pass-parallel operation. Therefore, we propose a highly parallel and memory efficient EBCOT architecture. The overall architecture wastes no clock cycle during the course of encoding and improves the processing speed by more than 80% compared with the previous methods.
Finally, a prototyping chip of block-coding engine is implemented in UMC 0.18um 1P6M technology. The chip area is 1210 x 620 (um). Simulation results show that the maximum operation frequency is 100 MHz and the average power dissipation is 78.4 mW.
URI: http://hdl.handle.net/11455/7325
Appears in Collections:電機工程學系所

Show full item record
 

Google ScholarTM

Check


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.