Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/7334
標題: 運用次臨界特性之低電壓CMOS參考電壓電路設計
Design of Low-Voltage CMOS Voltage Reference Circuits Based on Sub-threshold Characteristics
作者: 張登堪
Chang, Dern-kan
關鍵字: Bandgap voltage;能隙電壓;Current source generator;Subthreshold region;Voltage reference;電流源產生器;次臨界區;參考電壓
出版社: 電機工程學系所
引用: [1] I. M. Filanovsky and A. Allam, “Mutual compensation of mobility and threshold voltage temperature effects with applications in CMOS circuits,”IEEE Trans. Circuits Syst. I, vol. 48, pp. 876-884, July 2001. [2] G. Giustolisi, G. Palumbo, M. Criscione, and F. Cutrì, “A Low-Voltage Low-Power Voltage Reference Based on Subthreshold MOSFETs,” IEEE J. Solid-State Circuits, vol. 38, no. 1, pp. 151-154, 2003. [3] Behzad Razavi,“Design of Analog CMOS Integrated Circuit,”NY:McGraw-Hill, 2001 [4] D. Hilbiber “A new Semiconductor voltage standard,” in ISSCC Dig. Tech. Papers, pp. 32-33, Feb. 1964 [5] R. M. Swanson and J. D. Meindl, “Ion-implanted complementary MOS transistor in low-voltage circuits,” ZEEE J. Solid-State Circuits, vol. SC-7, pp. 146-153, Apr. 1972. [6] Y. Cheng and C. Hu, MOSFET Modeling & BSIM3 User's Guide, New York: Kluwer, 1999. [7] Willy M.C. Sansen, “Analog Design Essentials” Springer 2006 [8] Eric Vittoz, and Jean Fellrath, “CMOS Analog Integrate Circuit Based on Weak Inversion Operation” IEEE J. Solid-State Circuits, vol. sc-12 no.3, pp. 224-231, June 1977. [9] Oguey H J, Aenischer D.”CMOS Current Reference Without Resistance” IEEE J SSC,1997. [10] P.-H. Huang, H. Lin, and Y.-T. Lin, “A Simple Subthreshold CMOS Voltage Reference Circuit with Channel Length Modulation Compensation,” IEEE Trans. Circuits and Systems II (in press) [11] Hironori Banba, Hitoshi Shiga, Akira Umezawa, Takeshi Miyaba, Toru Tanzawa, Shigeru Atsumi, and Koji Sakui, “A CMOS Bandgap Reference Circuit With Sub-1-V Operation” IEEE J. Solid-State Circuits, vol. 34, pp. 670-673, May 1999. [12]H. Lin, D.K chang , “A Low- Voltage Process Corner Insensitive Subthreshold CMOS Voltage Reference Circuit,” ICICDTO6 [13] P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Ci~cuits. New York: Wiley, 1977.
摘要: 
傳統能隙參考電壓電路通常需要很高的供應電壓。為了因應低電壓的操作趨勢,許多人嘗試著使用場效電晶體的次臨界特性來產生參考電壓。然而,參考電壓對於不同的製程卻有著很大的變化,且電阻的運用所帶來的大面積。本論文將介紹兩種參考電壓電路來解決這些問題。
首先,提出第一個參考電壓電路,使用0.18um CMOS製程技術且運用CMOS電晶體的特性,使其工作在次臨界區,藉以產生一個穩定的參考電壓值約278mV。其供應電壓範圍從0.8V 變化到 2.6V,而總電流消耗值大約是3.6uA。為了減少臨界電壓隨製程變異所產生電壓變化,其解決之道,使用了一個 Normal NMOS 和 ㄧ個 High-threshold NMOS ,利用之間的特性去做補償。同時,通道長度調變效應也是作為補償。而整體電路所佔據的面積值約 0.04 mm 2,其參考電壓在不同製程下變化,大概是 2.5mV,而溫度變化範圍從-20 度C 到 120度C。
接著提出一個無電阻參考電壓電路,使用0.18um CMOS製程技術提供了一個穩定的電壓值約101mV,其供應電壓範圍從0.9V 變化到 2.6V,而總電流消耗值大約是7.4uA。使用兩個NMOS電晶體當作電阻,而其電阻值可以當作溫度變化效應的補償。其參考電壓在不同製程下變化,大概是 2.5mV,而溫度變化範圍從-10度C 到 110度C,整體電路所佔據的面積值約 0.0122 mm 2。

The conventional band-gap reference voltage circuits usually require high supply voltage. To comply with the trend of low voltage operations, many people have tried to use the sub-threshold characteristics to generate the reference voltage. However, they may suffer from larger corner variations or larger chip area due to the resistors in the circuits. This thesis introduces two voltage reference circuits to alleviate these problems.
The first voltage reference circuit is presented for generating a constant reference voltage of 278mV using sub-threshold characteristics of 0.18um CMOS technology at supply voltages from 0.8V to 2.6V with a total current of 3.6 uA. The threshold voltage variation due to process corner variation is minimized by a threshold voltage tracking technique between the normal and high threshold NMOS transistors. In the mean time, channel-length modulation effect is also compensated. The proposed circuit on the chip area of 0.04mm 2 achieves the total reference voltage variation of 2.5mV for various process corners and temperature variation from -20 degree C to 120 degree C.
The second voltage reference without the resistor providing a constant voltage reference of 101mV was realized in 0.18um CMOS technology at supply voltage from 0.9V to 2.6V with a total current of 7.4uA. There are two NMOS transistors used as resistors. The resistance ratio can be compensated to cancel temperature variation effects to achieve a nearly constant voltage reference. For temperatures from -10 degree C to 110 degree C, it has a variation about 2mV with different process corners, in chip area of 0.0122mm 2.
URI: http://hdl.handle.net/11455/7334
其他識別: U0005-0308200713045700
Appears in Collections:電機工程學系所

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