Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/7336
標題: 應用於高速串列傳輸之1.25-Gb/s時脈資料回復電路
A 1.25-Gb/s Clock and Data Recovery Circuit for High-Speed Serial Links
作者: 李承興
Lee, Cheng-Hsing
關鍵字: Clock and Data Recovery Circuit;時脈資料回覆電路;Phase-Locked loop;鎖相迴路
出版社: 電機工程學系
摘要: 
時脈和數據回復電路(CDR)在串列傳輸器中為一個重要元件。在高性能通信系統中,高速低功率時脈和數據回復電路一直很廣泛的使用。因為進步的數位信號處理往往需要數據資料的時序消息,而時脈和數據回復電路正可以將其時脈找出來,並且藉由判斷電路將數據資料的時序決定。
本論文使用TSMC 0.35μm 2P4M CMOS製程實現一個1.25-Gb/s時脈和數據回復電路。相位偵測是時脈和數據回復電路的一個重要元件,必須正確的處理非週期性訊號,如隨機不歸零資料。我們提出了一個可處理隨機不歸零資料的新型相位偵測器,此電路可有效的減少死帶的問題。以鎖相迴路架構為基礎,時脈和數據回復電路能夠從隨機不歸零資料中取出時脈並且決定數據資料的時序。此時脈和數據回復電路晶片在3V供應電源的消耗功率為64.8mW,其晶片有效面積為1216μm×852μm。
在高速電路中,為了減少壓控振盪器(VCO)的設計難度,且得到較佳的調諧範圍,可採用VCO操作於半速率的時脈和數據回復電路。最後,我們利用一個新型的半速率相位偵測器,設計出半速率時脈和數據回復電路,電路鎖定之後,可得二組625Mb/s的資料列。

Clock and data recovery (CDR) circuit is a key-point component in serial links. High-speed low-power CDR circuits find wide application in high-performance communication systems. Since further digital processing requires timing information on the data, a CDR circuit extracts the clock and a decision circuit retimes the data. The following data processing can thus be performed synchronously.
A 1.25Gb/s CDR circuit has been fabricated in TSMC 0.35-μm 2P4M CMOS process. Each blocks of this circuit are discussed in detail. The phase detector plays a critical role in determining the purity of the CDR from the recovered data and directly applicable to the data stream with missing pulses such as random NRZ data. A new phase detector applicable to the 1.25-Gb/s NRZ data stream is adopted to reduce the dead zone in phase characteristic. This chip dissipates a power of 64.8mW at 3V supply voltage and occupies an active area 1216μm × 852μm.
At very high speed, it may be difficult to design an oscillator that provides an adequate tuning range with reasonable jitter. For this reason, CDR circuits may sense the input random data at full rate but employ a VCO running at half the input data. A half-rate phase detector is designed for a half-rate clock and data recovery circuit in this thesis. At lock condition, the circuit will generate two 625-Mb/s output sequences.
URI: http://hdl.handle.net/11455/7336
Appears in Collections:電機工程學系所

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