Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/7350
標題: 一個六位元每秒二十億次取樣率之快閃式類比數位轉換器
A 6-bit 2-GS/sec Flash Type Analog-to-Digital Converter
作者: 蕭志奕
Hsiao, Chih-Yi
關鍵字: 快閃式;Flash ADC;類比數位轉換器
出版社: 電機工程學系所
引用: [1] M. Choi and A. A. Abidi, “A 6b 1.3Gsample/ s A/D converter in 0.35μm CMOS,”IEEE J. SolidState Circuits, vol. 36, no. 12, pp.18471858, Dec. 2001. [2] Iuri Megr and Declan Dalton, ”A 500-MSample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel Applications” IEEE J. Solid-State Circuits, vol. 34, no. 7, pp. 912-920, Jul. 1999. [3] Yuko Tamba and Kazuo Yamakido, ”A CMOS 6b 500MSample/s ADC for a Hard Disk Drive Read Channel,” in IEEE Int. Solid-State Circuits Conf. (ISSCC), pp. 324-325, Feb. 2000. [4] L. Rong, E. Martin, I.Gustafsson, A. Rusu, M.Ismail, ”System Design of a Flash ADC for UWB Applications” IEEE International Symposium on Quality Electronic Design, 2007. [5] Jun-Xia Ma, Sai-Weng Sin, Seng-Pan U Martins, “A Power-efficient 1.056 GS/s resolution-switchable 5-bit/6-bit flash ADC for UWB applications”, IEEE International Symposium on Circuits and Systems 2006 [6] M. Burns, G. W. Roberts, “An Introduction to Mixed-Signal IC Test and Measurement,” Oxford University Press, Inc. Published, 2001. [7] P. E. Allen, “CMOS analog circuit design -2nd ed.” Oxford University Press, Inc. 2002 [8] R. Van de Plassche, Integrated Analog-To-Digital and Digital-To-Analog Converters. Boston, MA: Kluwer, 2003 [9] W. Black and D. Hodges, “Time interleaved converter arrays,” IEEE J. Solid-State Circuits, vol. SC-15, no. 12, pp. 1022–1029, Dec. 1980. [10] B. Razavi, “Design of Analog CMOS Integrated Circuits”. [11] B.Razavi, B. A. Wooley,“Design Techniques for High-speed, High- Resolution Comparators”, IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 27. NO. 12. DECEMBER 1992 [12] B. Razavi, “Principles of Data Conversion System Design”, IEEE Press, 1995. [13] 林凱琪,高速快閃式類比數位轉換器,台北科技大學電腦通訊與控制研究所碩士學位論文,2002 [14] B. Razavi, “Principles of Data Conversion System Design”, IEEE Press, 1995. - 68 - [15] S. Park, Y. Palaskas, and M. P. Flynn, “A 4GS/s 4b flash ADC in 0.18μm CMOS,” International Solid-State Circuits Conference, Feb. 2006 [16] P. Scholtens and M. Vertregt, ”A 6b 1.6GSample/s flash ADC in 0.18μm CMOS using averaging termination,” IEEE Int. SolidState Circuits Conf, pp.168169, Feb 2002. [17] P. M. Figueiredo and J. C. Vital, “Termination of averaging networks in flash ADCs,”in Proc. 2004 Int. Symp. Circuits and Systs., vol. 1, May 2004, pp. 121–124. [18] H. Okada, Y. Hashimoto, K. Sakata, T. Tsukada, and K. Ishibashi, “Offset calibrating comparator array for 1.2-V, 6-bit, 4-Gsample/s flash ADCs using 0.13-um CMOS technology,” in Proc. ESSCIRC’03, Sep. 2003, pp. 711–714. [19] J. Vandenbussche, K. Uyttenhove, E. Lauwers, M. Steyaert and G. Gielen, “A 8-bit 200 MS/s Interpolating/Averaging CMOS A/D Converter”, IEEE CICC, 2002. [20] X. Jiang and M.-C. F. Chang, “A 1-GHz signal bandwidth 6-bit CMOS ADC with power-efficient averaging,” IEEE J. Solid-State Circuits,vol.40 , pp. 532–535, Feb.2005. [21] Michael P. Flynn and David J. Allstot, ”CMOS Folding A/D Converters with Current-Mode Interpolation,” IEEE J. Solid-State Circuits, vol. 31, no.9, pp. 1248-1257, Sep. 1996. [22] C. Sandner et al., “A 6-bit 1.2-GS/s Low-Power Flash-ADC in 0.13-um Digital CMOS,” IEEE J. Solid-State Circuits, vol. 40, pp. 1499-1505, Jul. 2005. [23] R. Van de Plassche, Integrated Analog-To-Digital and Digital-To-Analog Converters. Boston, MA: Kluwer, 2003 [24] O.Viitala, S.Lindfors and K.Halonen, “A 5-bit 1-GS/s Flash-ADC in 0.13-um CMOS Using Active Interpolation,”ISSCIR 2006 [25] R. Van de Plassche, Integrated Analog-To-Digital and Digital-To-Analog Converters. Boston, MA: Kluwer, 2003 [26] K. Uyttenhove, A. Marques, and M. Steyaert, “A 6-bit 1 GHz acquisition speed CMOS flash ADC with digital error correction,” in Proc. IEEE Custom Integrated Circuits Conf., May 2000, pp. 249–252 [27] M. Choi and A. A. Abidi, “A 6b 1.3Gsample/ s A/D converter in 0.35μm CMOS,”IEEE J. SolidState Circuits, vol. 36, no. 12, pp.18471858, Dec. 2001. - 69 - [28] K. Uyttenhove and M. S. J. Steyaert, “A 1.8V 6Bit 1.3GHz flash ADC in 0.25um CMOS,” IEEE J. SolidState Circuits, vol. 38, no.7,pp.1115– 1122, July 2003. [29] B. Razavi, “Design of Analog CMOS Integrated Circuits”. [30] S. Sheikhaei, S. Mirabbasi, A. Ivanov, “A 4-bit 5GS/s flash A/D converter in 0.18μm CMOS,” IEEE International Symposium on Circuits and Systems, May 2005. [31] M. Burns, G. W. Roberts, “An Introduction to Mixed-Signal IC Test and Measurement,” Oxford University Press, Inc. Published, 2001.
摘要: 
由於製程技術的進步,CMOS 積體電路的操作頻率也隨著增加。因此在類比與數位之間的介面也需要操作在極高的速度。高速類比數位轉換器被廣泛的應用在磁碟讀取通道、高速量測系統和超寬頻接收器的通
訊系統中。
在此論文中,實現了一個取樣速率為每秒二十億次,六位元之快閃式類比數位轉換器。發生於類比數位轉換器前端之偏差電壓常導致輸出端的非線性誤差。因此我們應用了可修正偏差電壓的方法來改善此類比數位轉換器之效能。為了降低快閃式類比轉換器的輸入電容和偏差修正電路的數量,我們應用了主動式內插技術。模擬結果顯示此類比數位轉換器之信號-雜訊失真比(SNDR)在取樣速率2 GS/s,輸入訊號為100MHz時可達36dB,在輸入訊號為951MHz時可達到34dB。功率消耗在取樣頻率2 GS/s和1.8伏特電源供應時為650毫瓦。此晶片的面積為1.96-mm2,由TSMC 0.18-um 1P6M
CMOS製程所製造。

The operating frequency of integrated circuits has been increasing due to the advance process technologies. Thus the interfaces between the analog and the digital parts require to operate at ultra high speed. High-speed ADCs are widely used for the applications in disk drive read channels, high-speed measurement systems, and
communication systems such as UWB receivers.
In this thesis, A 2-GS/s 6-bits flash A/D converter(ADC) is implemented. Offset voltage in front-end of ADC usually results in nonlinearity in the outputs. Thus an offset calibrating method is applied to improve the performance of the ADC. To reduce the input capacitance of the flash ADC and the amount of the calibration circuit, the active interpolation technique is applied. Simulation results show the ADC achieves a SNDR of 36 dB for a 100 MHz input at 2 GS/s, and 34 dB for a 951-MHz input. The power consumption is 650 mW at 2 GS/s from a 1.8-V supply. The chip
occupies 1.96-mm2 active area, fabricated in TSMC 0.18-um 1P6M CMOS.
URI: http://hdl.handle.net/11455/7350
其他識別: U0005-0410200720585900
Appears in Collections:電機工程學系所

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