Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/7350
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dc.contributor張振豪zh_TW
dc.contributor許恒壽zh_TW
dc.contributor.advisor楊清淵zh_TW
dc.contributor.author蕭志奕zh_TW
dc.contributor.authorHsiao, Chih-Yien_US
dc.contributor.other中興大學zh_TW
dc.date2008zh_TW
dc.date.accessioned2014-06-06T06:39:57Z-
dc.date.available2014-06-06T06:39:57Z-
dc.identifierU0005-0410200720585900zh_TW
dc.identifier.citation[1] M. Choi and A. A. Abidi, “A 6b 1.3Gsample/ s A/D converter in 0.35μm CMOS,”IEEE J. SolidState Circuits, vol. 36, no. 12, pp.18471858, Dec. 2001. [2] Iuri Megr and Declan Dalton, ”A 500-MSample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel Applications” IEEE J. Solid-State Circuits, vol. 34, no. 7, pp. 912-920, Jul. 1999. [3] Yuko Tamba and Kazuo Yamakido, ”A CMOS 6b 500MSample/s ADC for a Hard Disk Drive Read Channel,” in IEEE Int. Solid-State Circuits Conf. (ISSCC), pp. 324-325, Feb. 2000. [4] L. Rong, E. Martin, I.Gustafsson, A. Rusu, M.Ismail, ”System Design of a Flash ADC for UWB Applications” IEEE International Symposium on Quality Electronic Design, 2007. [5] Jun-Xia Ma, Sai-Weng Sin, Seng-Pan U Martins, “A Power-efficient 1.056 GS/s resolution-switchable 5-bit/6-bit flash ADC for UWB applications”, IEEE International Symposium on Circuits and Systems 2006 [6] M. Burns, G. W. Roberts, “An Introduction to Mixed-Signal IC Test and Measurement,” Oxford University Press, Inc. Published, 2001. [7] P. E. Allen, “CMOS analog circuit design -2nd ed.” Oxford University Press, Inc. 2002 [8] R. Van de Plassche, Integrated Analog-To-Digital and Digital-To-Analog Converters. Boston, MA: Kluwer, 2003 [9] W. Black and D. Hodges, “Time interleaved converter arrays,” IEEE J. Solid-State Circuits, vol. SC-15, no. 12, pp. 1022–1029, Dec. 1980. [10] B. Razavi, “Design of Analog CMOS Integrated Circuits”. [11] B.Razavi, B. A. Wooley,“Design Techniques for High-speed, High- Resolution Comparators”, IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 27. NO. 12. DECEMBER 1992 [12] B. Razavi, “Principles of Data Conversion System Design”, IEEE Press, 1995. [13] 林凱琪,高速快閃式類比數位轉換器,台北科技大學電腦通訊與控制研究所碩士學位論文,2002 [14] B. Razavi, “Principles of Data Conversion System Design”, IEEE Press, 1995. - 68 - [15] S. Park, Y. Palaskas, and M. P. Flynn, “A 4GS/s 4b flash ADC in 0.18μm CMOS,” International Solid-State Circuits Conference, Feb. 2006 [16] P. Scholtens and M. Vertregt, ”A 6b 1.6GSample/s flash ADC in 0.18μm CMOS using averaging termination,” IEEE Int. SolidState Circuits Conf, pp.168169, Feb 2002. [17] P. M. Figueiredo and J. C. Vital, “Termination of averaging networks in flash ADCs,”in Proc. 2004 Int. Symp. Circuits and Systs., vol. 1, May 2004, pp. 121–124. [18] H. Okada, Y. Hashimoto, K. Sakata, T. Tsukada, and K. Ishibashi, “Offset calibrating comparator array for 1.2-V, 6-bit, 4-Gsample/s flash ADCs using 0.13-um CMOS technology,” in Proc. ESSCIRC’03, Sep. 2003, pp. 711–714. [19] J. Vandenbussche, K. Uyttenhove, E. Lauwers, M. Steyaert and G. Gielen, “A 8-bit 200 MS/s Interpolating/Averaging CMOS A/D Converter”, IEEE CICC, 2002. [20] X. Jiang and M.-C. F. Chang, “A 1-GHz signal bandwidth 6-bit CMOS ADC with power-efficient averaging,” IEEE J. Solid-State Circuits,vol.40 , pp. 532–535, Feb.2005. [21] Michael P. Flynn and David J. Allstot, ”CMOS Folding A/D Converters with Current-Mode Interpolation,” IEEE J. Solid-State Circuits, vol. 31, no.9, pp. 1248-1257, Sep. 1996. [22] C. Sandner et al., “A 6-bit 1.2-GS/s Low-Power Flash-ADC in 0.13-um Digital CMOS,” IEEE J. Solid-State Circuits, vol. 40, pp. 1499-1505, Jul. 2005. [23] R. Van de Plassche, Integrated Analog-To-Digital and Digital-To-Analog Converters. Boston, MA: Kluwer, 2003 [24] O.Viitala, S.Lindfors and K.Halonen, “A 5-bit 1-GS/s Flash-ADC in 0.13-um CMOS Using Active Interpolation,”ISSCIR 2006 [25] R. Van de Plassche, Integrated Analog-To-Digital and Digital-To-Analog Converters. Boston, MA: Kluwer, 2003 [26] K. Uyttenhove, A. Marques, and M. Steyaert, “A 6-bit 1 GHz acquisition speed CMOS flash ADC with digital error correction,” in Proc. IEEE Custom Integrated Circuits Conf., May 2000, pp. 249–252 [27] M. Choi and A. A. Abidi, “A 6b 1.3Gsample/ s A/D converter in 0.35μm CMOS,”IEEE J. SolidState Circuits, vol. 36, no. 12, pp.18471858, Dec. 2001. - 69 - [28] K. Uyttenhove and M. S. J. Steyaert, “A 1.8V 6Bit 1.3GHz flash ADC in 0.25um CMOS,” IEEE J. SolidState Circuits, vol. 38, no.7,pp.1115– 1122, July 2003. [29] B. Razavi, “Design of Analog CMOS Integrated Circuits”. [30] S. Sheikhaei, S. Mirabbasi, A. Ivanov, “A 4-bit 5GS/s flash A/D converter in 0.18μm CMOS,” IEEE International Symposium on Circuits and Systems, May 2005. [31] M. Burns, G. W. Roberts, “An Introduction to Mixed-Signal IC Test and Measurement,” Oxford University Press, Inc. Published, 2001.zh_TW
dc.identifier.urihttp://hdl.handle.net/11455/7350-
dc.description.abstract由於製程技術的進步,CMOS 積體電路的操作頻率也隨著增加。因此在類比與數位之間的介面也需要操作在極高的速度。高速類比數位轉換器被廣泛的應用在磁碟讀取通道、高速量測系統和超寬頻接收器的通 訊系統中。 在此論文中,實現了一個取樣速率為每秒二十億次,六位元之快閃式類比數位轉換器。發生於類比數位轉換器前端之偏差電壓常導致輸出端的非線性誤差。因此我們應用了可修正偏差電壓的方法來改善此類比數位轉換器之效能。為了降低快閃式類比轉換器的輸入電容和偏差修正電路的數量,我們應用了主動式內插技術。模擬結果顯示此類比數位轉換器之信號-雜訊失真比(SNDR)在取樣速率2 GS/s,輸入訊號為100MHz時可達36dB,在輸入訊號為951MHz時可達到34dB。功率消耗在取樣頻率2 GS/s和1.8伏特電源供應時為650毫瓦。此晶片的面積為1.96-mm2,由TSMC 0.18-um 1P6M CMOS製程所製造。zh_TW
dc.description.abstractThe operating frequency of integrated circuits has been increasing due to the advance process technologies. Thus the interfaces between the analog and the digital parts require to operate at ultra high speed. High-speed ADCs are widely used for the applications in disk drive read channels, high-speed measurement systems, and communication systems such as UWB receivers. In this thesis, A 2-GS/s 6-bits flash A/D converter(ADC) is implemented. Offset voltage in front-end of ADC usually results in nonlinearity in the outputs. Thus an offset calibrating method is applied to improve the performance of the ADC. To reduce the input capacitance of the flash ADC and the amount of the calibration circuit, the active interpolation technique is applied. Simulation results show the ADC achieves a SNDR of 36 dB for a 100 MHz input at 2 GS/s, and 34 dB for a 951-MHz input. The power consumption is 650 mW at 2 GS/s from a 1.8-V supply. The chip occupies 1.96-mm2 active area, fabricated in TSMC 0.18-um 1P6M CMOS.en_US
dc.description.tableofcontents誌謝 - - - - - - - - - - - - - - - - - - - - - - - -i 摘要(中文) - - - - - - - - - - - - - - - - - - - - ii 摘要(英文) - - - - - - - - - - - - - - - - - - - - -iii 目錄 - - - - - - - - - - - - - - - - - - - - - - iv 第一章 緒論 1.1研究動機 1 1.2內容編排 2 第二章 類比數位轉換器簡介 2.1 類比數位轉換器理論及參數介紹 2.1.1 解析度 3 2.1.2 取樣定理 3 2.1.3 量化誤差 4 2.1.4 信號雜訊失真比(SNDR) 5 2.1.5 無雜散動態範圍(SFDR) 6 2.1.6 動態範圍 7 2.1.7 靜態特性 7 2.2 類比數位轉換器架構回顧 2.2.1 簡介 10 2.2.2 快閃式類比數位轉換器 11 2.2.3 二階段式類比數位轉換器 13 2.2.4 管線式類比數位轉換器 14 2.2.5 摺疊式類比數位轉換器 16 2.2.6 分時並行式類比數位轉換器 17 2.2.7 討論 18 第三章 2GS/s,6位元快閃式類比數位轉換器之設計 3.1 前言 19 3.2 類比數位轉換器系統架構 23 3.3 內插電路 26 3.4 參考電壓產生器 31 3.5 前置放大器 34 3.6 拴鎖器 35 3.7 偏差電壓校正電路 37 3.8 解碼器 42 3.9 傳輸閘及多工器 46 3.10 時脈緩衝器 47 第四章 類比數位轉換器之模擬、佈局及測量 4.1 INL與DNL之模擬 48 4.2 SNDR之模擬 51 4.3 晶片之佈局考量 57 4.4 晶片之量測 59 第五章 結論 5.1 結論 65 5.2 討論及未來展望 65 參考文獻 67 附錄 圖目錄 圖1.1 訊號處理示意圖 1 圖1.2 UWB Receiver 2 圖2.1 交疊效應示意圖 4 圖2.2 量化誤差示意圖 5 圖2.3 量化誤差機率密度函數 5 圖2.4 SFDR示意圖 6 圖2.5 動態範圍 7 圖2.6 非理想效應在轉換曲線中呈現 8 圖2.7 INL與DNL 9 圖2.8 三位元快閃式類比數位轉換器 12 圖2.9 兩階段式原理 13 圖2.10 八位元兩階段式類比數位轉換器 14 圖2.11 管線式類比數位轉換器架構 15 圖2.12 摺疊式類比數位轉換器方塊圖 16 圖2.13 訊號摺疊示意圖 16 圖2.14 分時並行式類比數位轉換器 17 圖2.15 分時並行式類比數位轉換器控制時序訊號 18 圖3.1 比較器架構圖 19 圖3.2 泡沫錯誤示意圖 21 圖3.3 不穩態錯誤示意圖 22 圖3.4 泡沫錯誤之消除 23 圖3.5 類比數位轉換器整體架構 24 圖3.6 控制訊號時序圖 25 圖3.7 降頻取樣電路 25 圖3.8 降頻取樣示意圖 25 圖3.9 降頻取樣模擬圖 26 圖3.10 電壓式內插 27 圖3.11 電流式內插 28 圖3.12 電容式內插 29 圖3.13 主動式內插 29 圖3.14 快閃式類比數位轉換器 30 圖3.15 類比數位轉換器六位元輸出模擬圖 30 圖3.16 饋通效應示意圖 31 圖3.17 電阻串及輸入電容等效模型 32 圖3.18 全差動架構對於電阻串的影響 33 圖3.19 全差動之電阻串及輸入電容等效模型 33 圖3.20 前置放大器電路圖 34 圖3.21 (a)無reset開關,(b)有reset開關 35 圖3.22 前置放大器頻率響應圖 35 圖3.23 拴鎖器電路 36 圖3.24 拴鎖器之Reset模式 36 圖3.25 拴鎖器之 Regeneration模式 37 圖3.26 拴鎖器模擬圖 37 圖3.27 (a)偏差電壓與DNL關係圖(b)偏差電壓與INL關係圖 38 圖3.28 理想比較器轉換曲線 39 圖3.29 比較器之蒙地卡羅模擬圖 39 圖3.30 偏差電壓校正電路圖 40 圖3.31 控制邏輯 41 圖3.32 四位元計數器 41 圖3.33 校正電路模擬圖 41 圖3.34 (a)CML之NAND及AND (b)CML之XOR 44 圖3.35 解碼器 45 圖3.36 傳輸閘及其等效模型 46 圖3.37 時脈緩衝器電路 47 圖4.1 Histogram 圖 48 圖4.2 實際 Histogram圖 50 圖4.3 無偏差校正之DNL與INL 50 圖4.4 有偏差校正之DNL與INL 51 圖4.5 (a) 正確之FFT (b) 錯誤之FFT 52 圖4.6 fin=291MHz之SNDR 53 圖4.7 fin=490MHz之SNDR 53 圖4.8 fin=951MHz之SNDR 53 圖4.9 fin=291MHz之SNDR(無校正) 54 圖4.10 fin=490MHz之SNDR(無校正) 54 圖4.11 fin=951MHz之SNDR(無校正) 54 圖4.12 類比數位轉換器之SNDR 54 圖4.13 Corner SS 55 圖4.14 Corner TT 55 圖4.15 Corner FF 55 圖4.16 晶片佈局圖 58 圖4.17 量測配置圖 59 圖4.18 晶片及PCB照相圖 59 圖4.19 量測儀器 60 圖4.20 fin=7MHz 60 圖4.21 fin=108MHz 61 圖4.22 fin=211MHz 61 圖4.23 數位訊號還原後之波形 61 圖4.24 fin對SNDR曲線圖 62 圖4.25 DNL and INL 62 圖4.26 48PIB接腳圖 63 表目錄 表2.1 類比數位轉換器的分類及架構 11 表3.1 三種數位碼對照表(3bits) 42 表4.1 模擬規格列表 56 表4.2 快閃式類比轉換器比較表 56 表4.3 量測效能總結 63 表4.4 各接腳圖之說明 64zh_TW
dc.language.isoen_USzh_TW
dc.publisher電機工程學系所zh_TW
dc.relation.urihttp://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-0410200720585900en_US
dc.subject快閃式zh_TW
dc.subjectFlash ADCen_US
dc.subject類比數位轉換器zh_TW
dc.title一個六位元每秒二十億次取樣率之快閃式類比數位轉換器zh_TW
dc.titleA 6-bit 2-GS/sec Flash Type Analog-to-Digital Converteren_US
dc.typeThesis and Dissertationzh_TW
item.openairecristypehttp://purl.org/coar/resource_type/c_18cf-
item.openairetypeThesis and Dissertation-
item.cerifentitytypePublications-
item.fulltextno fulltext-
item.languageiso639-1en_US-
item.grantfulltextnone-
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