Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/7401
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dc.contributor.advisor張振豪zh_TW
dc.contributor.advisorChen-Hao Changen_US
dc.contributor.author洪柏鍾zh_TW
dc.contributor.authorHung, Po-Chungen_US
dc.date2001zh_TW
dc.date.accessioned2014-06-06T06:40:00Z-
dc.date.available2014-06-06T06:40:00Z-
dc.identifier.urihttp://hdl.handle.net/11455/7401-
dc.description.abstract由於可攜式電子裝備的需求量與其所要求的效能,包括運算能力與使用時間,不斷地提升;低功率便成為在積體電路設計領域的重要理念。絕熱式邏輯電路(或稱為能量回收式電路)為一種降低功率消耗的設計方式。其使用絕熱式充放電的方式可以突破傳統互補式金屬氧化半導體(CMOS)操作方式,有CV2能量消耗產生的障礙。絕熱式電路所消耗的能量可分為兩種:絕熱能耗與非絕熱能耗。絕熱能耗在絕熱式邏輯中是不能消除的。但一般絕熱式邏輯都只能降低一部份非絕熱能耗。本論文分析產生非絕熱能耗的原因,且提出四種使用提升電壓及電荷回收利用技術的絕熱式電路。經由模擬一個八位元進位前瞻加法器可得知我們所提出的能量回收式互補傳輸邏輯(ERCPL)可比傳統CMOS電路減少84.4%的功率消耗。zh_TW
dc.description.abstractDue to the increasing demand of portable equipments and their capability, including computational power and reliability, reducing power consumption has become an important aspect in the field of integrated circuits design. Adiabatic logic (or so called energy recovery logic) is a design style to reduce power consumption. The rule of adiabatic switching can circumvent the CV2 barrier of dissipated energy which is generated by operating CMOS circuits in a conventional way. The energy dissipated in adiabatic circuits can be distinguished into two kinds: adiabatic loss and non-adiabatic loss. An adiabatic circuit can't avoid adiabatic loss. But adiabatic logics usually can only reduce part of non-adiabatic loss. This thesis explains the reason of existence of adiabatic loss, and proposes four kinds of new adiabatic logics which use bootstrapping and charge recycling techniques. Simulation results of an 8-bit carry look-ahead adder show that the Energy Recovery Complementary Pass-transistor Logic we proposed can saves 84.4% power dissipation compared to conventional CMOS dissipation.en_US
dc.description.tableofcontentsChapter 1. Introduction..........................1 1.1 Motivation...................................1 1.2 Adiabatic Switching..........................2 1.2.1 Conventional CMOS Energetics...............2 1.2.2 Adiabatic Switching........................5 1.2.3 Classification of Energy Consumption.......7 1.3 Adiabatic Circuit Design Issues..............9 1.3.1 Retractile Cascade.........................9 1.3.2 Classification of Adiabatic Circuit.......11 1.4 Organization of Thesis......................12 Chapter 2. Previous Adiabatic Logics............13 2.1 2N-2N2D.....................................13 2.1.1 Operation of 2N-2N2D......................13 2.1.2 Power Dissipation in 2N-2N2D..............14 2.2 ECRL........................................14 2.2.1 Operation of ECRL.........................15 2.2.2 Power Dissipation in ECRL.................16 2.3 NMOS Energy Recovery Logic..................17 2.3.1 Feature of NERL...........................17 2.3.2 The Reason to Use Bootstrapping...........17 2.3.3 Operation of NERL.........................18 2.3.4 Energy Dissipation of NERL................21 Chapter 3. Design of New Adiabatic Logics.......23 3.1 mNERL.......................................23 3.1.1 Construction of mNERL.....................23 3.1.2 Energy Dissipation of mNERL...............24 3.1.3 Simulation Results........................24 3.2 NERL-2N.....................................25 3.2.1 Construction of NERL-2N...................25 3.2.2 Operation of NERL-2N......................27 3.2.3 Energy Dissipation of NERL-2N.............29 3.2.4 Simulation Results........................29 3.3 ERCPL.......................................31 3.3.1 Constitution of ERCPL.....................31 3.3.2 Operation of ERCPL........................34 3.3.3 Charge Recycle in ERCPL...................36 3.4 ERCPL-2N....................................38 3.5 Simulation results..........................41 Chapter 4. Adiabatic Circuits ..................43 4.1 A pipelined Carry Look-Ahead Adder..........43 4.1.1 ERCPL Carry Look-Ahead Adder..............43 4.1.2 ERCPL-2N..................................46 4.1.3 NERL Carry Look-Ahead Adder...............47 4.1.4 Simulation Results........................49 4.2 Layout Consideration........................50 4.3 Measurement Results.........................55 Chapter 5. Conclusion...........................59 References......................................60en_US
dc.language.isoen_USzh_TW
dc.publisher電機工程學系zh_TW
dc.subjectadiabatic logicen_US
dc.subject絕熱式邏輯zh_TW
dc.subjectenergy recoveryen_US
dc.subjectlow poweren_US
dc.subject能量回收zh_TW
dc.subject低功率zh_TW
dc.title低功率能量回收式互補電晶體傳輸邏輯zh_TW
dc.titleLow Power Energy Recovery Complementaryen_US
dc.typeThesis and Dissertationzh_TW
item.openairecristypehttp://purl.org/coar/resource_type/c_18cf-
item.languageiso639-1en_US-
item.grantfulltextnone-
item.cerifentitytypePublications-
item.openairetypeThesis and Dissertation-
item.fulltextno fulltext-
Appears in Collections:電機工程學系所
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