Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/7409
標題: 高速無線區域網路之架構
Architecture for High Speed Wireless LAN
作者: 張永賢
Chang, Yung-Hsien
關鍵字: 無線區域網路;Wireless LAN;互補碼調變;CCK
出版社: 電機工程學系
摘要: 
由於現代人資訊需求量很高,除了資料傳輸、檔案傳送之外,甚者聲音、影像等即時傳送。然而IEEE 802.11所訂定的標準中僅提供1和2Mbps的傳輸速率,此傳輸速率已無法滿足現代人的需求。所以在1999年九月IEEE 802.11b標準的通過,延續直接序列展頻技術,採用新的調變方式─互補碼調變,額外地增加兩種較高的傳輸速率,分別是5.5和11Mbps。
在本論文中,除了針對高速無線區域網路之基頻處理器設計一包含傳送端及接收端之完整架構外,並在互補碼解調之相關器上提出一新的架構。此外,一些無線區域網路之關鍵技術,包含:通道特性之模擬、展頻技術、載波回復技術及對抗衰減通道技術等,在本論文中皆有說明及比較。
至於互補碼解調之相關器,藉由使用吾人所提出之兩階相關性運算,與傳統相關器比較,可降低75%之複雜度,而功率則可節省84.375%。

In the original IEEE 802.11 standard two data rate, 1 and 2Mbps, are provided. However, the data rates are too slow to support most general business requirements. Recognizing the critical need to support higher data transmission rates, the IEEE ratified the 802.11b standard for transmissions of up to 11Mbps by using complementary code keying (CCK) in September 1999.
In this thesis, the design of a high-speed wireless LAN baseband processor and a new architecture for correlator of CCK demodulation are proposed. Beside, some important technologies for wireless LAN including channel characteristic, spread spectrum, carrier recovery, and anti-fading are appeared and explained in this paper.
By using the new architecture for correlator of CCK demodulation, the complexity of correlator could be reduced effectively.
URI: http://hdl.handle.net/11455/7409
Appears in Collections:電機工程學系所

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