Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/7410
標題: 雙倍取樣100MS/s10位元之全雙端雙管線式 類比轉數位轉換器
Doubled Sampling 100MS/s 10 Bit Fully Differential Pipelined Analog to Digital Convert
作者: 陳柏予
Chen, Po-Yu
關鍵字: Pipelined;管線式
出版社: 電機工程學系所
引用: 參考文獻 [1] Data sheet of “PAS202B VGA color CMOS image sensor”, Pix Art Imaging Inc., pp.1-4, February 2001. [2] J.Doermberg , P.R. Gray and D.A. Hodges, “A 10-bit 5-Msample/s CMOS two-step flash ADC”,IEEE Journal of Solid-State Circuits, vol. 24 no.2,pp. 241-249 apr.1989 [3] D.A. Johns, K. Martin, “Analog integrated circuit design”, John Wiley & Sons Inc. , pp.513-516, 1997. [4] A. David , K. Martin,” Analog Integrated Circuit Design ”,John Wiley& Sons ,Inc,1997. [5] H. Nyquist , “Certain Topics in Telegraph Transmission Theory”, Trans. Am. Inst. Electr. Eng., vol. 47, pp. 617–644, Feb. 1924. [6] “IEEE Standard for Terminology and Test Methods for Analog-to-Digital Converters, Standard, Measurements”, IEEE Standard 1241-2000, Dec. 2000. [7] J. Doernberg, H.S. Lee, D. A. Hodges, “Full Speed Testing of A/D Converters” IEEE J. Solid-State Circuits, vol. 19, no. 6, pp. 820–827, Dec. 1984. [8] W. Yang, D. Kelly, I. Mehr, M. T. Sayuk, L. Singer, “A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist Input”, IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1931–1936, Dec. 2001. [9] Helsinki University of Technology Electronic Circuit Design Laboratory Report 35, Espoo 2002. [10] B. Murmann, EE315 Lecture, Stanford University. [11] B. E. Boser, EECS 247 Lecture, University of California at Berkeley. [12] T. Cho, “Low-Power Low-Voltage Analog-to-Digital Conversion Techniques using Pipelined Architecures” ,PhD Thesis, University of California, Berkeley, 1995. [13] R. Lotfi, M. Taherzadeh-Sani, M.Y. Azizi , O. Shoaei, “A low-power design methodology for high-resolution pipelined analog-to-digital converters”, ISLPED ''03, Aug. 2003, pp.334 – 339. [14] M. Shinagawa, Y. Akazawa, T. Wakimoto, “Jitter analysis of high-speed sampling systems”, IEEE J. Solid-State Circuits, Vol. 25, pp. 220 – 224, Feb. 1990. [15] K. Bult, G.J.G.M. Geelen,“A fast-settling CMOS op amp for SC circuits with 90-dB DC gain”,IEEE J. Solid-State Circuits, Vol. 25, pp. 1379 – 1384, Dec. 1990. [16] T.B. Cho, and P.R. Gray, “A 10 b 20 Msample/s 35 mW pipeline A/D converter”,IEEE J. Solid-State Circuits, Vol. 30, pp. 166–172, March 1995. [17] S.H. Lewis, H.S. Fetterman, G.F. Gross, and R. Ramachandran, “A 10-bit 20-Msample/s analog-to-digital converter” ,IEEE J. Solid State Circuits, 1992.
摘要: 
摘 要

為了設計高速CMOS 雙倍取樣雙管道線的類比/數位轉換器電路(100MS/s 10位元),信號從一3.0伏特擺動的100 MS/s,1-Vpp的取樣率,雜訊考量,使用全雙端雙倍取樣保持電路及全雙端MDAC電路是為必要。電路中使用共同分享的運算放大器電路,
使兩條管線的取樣保持電路及MDAC電路共用運算放大器。
這ADC的應用於高解析率感應器系統和無線通信。對於高速高解析度類比/數位轉換器電路,由於開關電容(SC)技術被使用在管線的架構,非常成功利用CMOS技術的特徵。藉由供給電壓和調節技術的影響分析,顯示好處在開關電容(SC)。運算放大器是為核心,SC電路在週邊建立組成。
全部類比電路是用全雙端 ,1Vpp輸入信號和3.0 V供給電壓。這晶片經由Hspice設計,佈局及製作並且測試完成。總晶片面積是1.5mm x1.5mm,在TSMC 0.18um 1P6M 3V CMOS技術完成晶片製作。 合標準的執行在轉換速度(100MHz)包括頂峰SNDR大約43分貝。最大的轉換速度(100MHz)的功率耗損是180 mW。

Abstract

The goal of this design is to develop a high-speed CMOS Pipelined ADC circuit (10-bit 100MS/s). The target specifications were set as follows: 10-bit resolution, a sampling rate is 100 MS/s, 1-Vpp differential signal swing from a 3.0-volt supply, The differential structure is almost a necessity in S/H and MDAC circuit.The two channels of double sampled pipelined ADC were share a common opamp. Let two S/H circuit and two MDACs circuit were share a common opamp .
The applications of this ADC are focused on the high resolution Sensor System and the wireless communications. Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies.
All analog circuits are fully differential with a 1Vpp input signal and 3.0V power
supply. This chip has been designed, laid out, fabricated, and tested completely. The total chip area is 1.4 x 1.4 mm in TSMC 0.18um 1P6M 3V CMOS logic technology. The measured performance included a peak SNDR about 43dB at conversion rate (100MHz). The power dissipation at the maximum conversion rate (100MHz) is 180mW.
URI: http://hdl.handle.net/11455/7410
其他識別: U0005-0701200822413700
Appears in Collections:電機工程學系所

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