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Design of a CMOS Frequency Synthesizer
傳統的射頻頻率合成器主要是以GaAs, Bipolar甚至以BiCMOS製程設計,因為這兩種製程在高頻有較好的驅動能力及特性,但是這些製程無法與矽製程的基頻電路整合在一起.為了滿足在無線市場上的需求低成本高整合度矽製成較適合設計.因此若互補式金氧半電晶體積體(CMOS Integrated Circuit)電路能實現,整個接收端電路可被整合在單一晶片上,成本將會節省很多.隨著金氧半電晶體之通道逐年縮減,互補式金氧半電晶體之射頻積體電路(CMOS RF-IC)已逐步能夠在今日之技術下實現,但仍然有許多的問題需要解決.單一晶片系統仍是一大挑戰.
本論文描述一個3.3伏2.4GHz互補式金氧半電晶體頻率合成器,主要由相頻偵測器(PFD),電荷充放式電路(CP),低通慮波器(LF),壓控振盪器(VCO)以及一個多係數可調除頻器.論文中,我們設計一個新的多係數除可調除頻器及相頻偵測.此晶片由CIC下線以TSMC 0.35mm 1P4M技術製成.
Conventional RF frequency synthesizer circuits were fabricated using GaAs, bipolar, or even BiCMOS technology on the base of larger driving ability and better RF characteristics. However, These two processes are not compatible to the typical CMOS process, which is used to implement the baseband circuits. In order to meet the potentially high demand for such wireless LAN products, low-cost silicon-based radio transceivers are preferred because of the capability of integration. Thus, if the CMOS RF circuits can be realized, the whole transceiver circuits can be integrated into a single chip, and the cost will be cut down significantly. With the channel length of CMOS transistor scaling down year by year, CMOS RF-ICs are practical today, but there are still a lot of difficulties unsolved. The goal toward one chip system is a major challenge.
This thesis describes a 3.3V 2.4GHz CMOS frequency synthesizer, which is composed of a phase/frequency detector (PFD), a charge-pump (CP), a low-pass filter (LF), a voltage-controlled oscillator (VCO) and a multi-modulus frequency divider (FD). In this thesis, we focus on the novel and simpler multi-modulus frequency divider and phase frequency detector (PFD) for 2.4GHz frequency synthesizers. The chip has been implemented using TSMC 1P4M technology
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