Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/7442
標題: 應用於H.264/AVC編碼器之高輸出率轉換與量 化處理單元架構設計
Architecture Design of the High Throughput Transform and Quantization Processing Unit for H.264/AVC
作者: 林育練
Lin, Yu-Lian
關鍵字: Transform;H.264/AVC;Quantization;H.264/AVC;轉換;量化
出版社: 電機工程學系所
引用: 1、中文部分 [1] 鄭煜霖,”FPGA 設計與實作高硬體效能的H.264/AVC量化處理 器”,國立中興大學論文,民國95年6月 [2] 郭其昌,”H.264先進編碼標準”,工研院電通所 2、英文部分 [3] I. Amer, W. Badawy, and G. Jullien, “A High-Performance Hardware Implementation of the H.264 Simplified 8x8 Transformation and Quantization Video Coding,” IEEE International Conference on Acoustics, Speech, and Signal Processing, Volume 2, Page(s):ii/1137 - ii/1140, 18-23 March 2005. [4] R.C. Kordasiewicz, and S. Shirani, “ASIC and FPGA Implementations of H.264 DCT and Quantization Blocks,” 2005 IEEE International Conference on Image Processing, Volume 3, Page(s):III - 1020-3, 11-14 Sept. 2005. [5] K. Suh, S. Park, and H. Cho, “An Efficient Hardware Architecture of Intra Prediction and TQ/IQIT Module for H.264 Encoder,” ETRI Journal, Volume 27, Number 5, October 2005. [6] Chih-Peng Fan and Yu-Lian Lin, “Implementations of Low-Cost Hardware Sharing Architectures for Fast 8x8 and 4x4 Integer Transforms in H.264/AVC,” IEICE Trans. on Fundamentals of Electronics Communications and Computer Sciences, vol.E90-A, no.2, 02 2007. (SCI、EI) [7] Joint Video Team (JVT) of ISO/IEC MPEG and ITU-T VCEG, “Draft ITU-T recommendation and final draft international standard of joint video specification (ITU-T rec. H.264 ISO/IEC 14496-10 AVC),” 2003 [8] Chih-Peng Fan, “Fast 2-Dimensional 8x8 Integer Transform Algorithm Design For H.264/AVC Fidelity Range Extensions,” IEICE Tran. on Information and Systems, vol.E89-D, no.12, December 2006. (SCI、EI) [9] Chih-Peng Fan , “Fast 2-Dimensional 4x4 Forward Integer Transform Implementation for H.264/AVC,” IEEE Trans. on Circuit and Systems, Part II, vol.53, no.3, pp.174-177, March 2006. (SCI、EI) [10] Chih-Peng Fan , “Cost-Effective Hardware Sharing Architectures Of Fast 8x8 and 4x4 Integer Transforms For H.264/AVC,” IEEE Asia Pacific Conference on Circuits and Systems, Singapore, 01 2006. (EI) [11] Chih-Peng Fan and Yu-Lin Cheng , “Unified and Fast 2-Dimensional 4x4 Transform Design for H.264/AVC Texture Coding,” International Symposium on Intelligent Signal Processing and Communications Systems , Hong Kong (Database: Compendex), 01 2005. (EI) [12] R.Kordasiewicz, and S. Shirani, “Hardware Implementation of the Optimized Transform and quantization Blocks of H.264,” Canadian Conference on Electrical and Computer Engineering, Volume 2, Page(s):943 – 946, 2-5, May 2004. [13] Y. Zeng, L. Cheng, G. Bi, and A.C. Kot, “Integer DCTs and Fast Algorithms,” Transactions on Signal Processing, IEEE, Volume 49, Issue 11, Page(s):2774 – 2782, Nov. 2001. [14] Heng-Yao Lin; Yi-Chih Chao; Che-Hong Chen; Bin-Da Liu; Jar-Ferr Yang, “Combined 2-D Transform and Tuantization Architectures for H.264 Video Coders”, IEEE International Symposium on Circuits and Systems, Vol. 2, pp.1802-1805, May 2005. [15] L. Z. Liu, Q. Lin, M. T. Rong, and J. Li, “A 2-D Forward/Inverse Integer Transform Processor of H.264 Based on Highly-Parallel Architecture,” Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Rime Applications (IWSOC''04).
摘要: 
達到降低面積最新一代的視訊壓縮標準H.264/AVC,其在視訊編碼演算法的改進,使得壓縮比及視訊品質都較以往的視訊標準有大幅度的提昇,對於高畫質數位電視(HDTV)或高畫質DVD都可以輕易的滿足其應用需求。但相對的會造成在編碼端複雜度的上昇,增加硬體實現的難度。
本論文中是針對H.264/AVC的整數轉換與量化探討,並實現其硬體。在整數轉換部份包含了4x4正逆整數轉換、8x8正逆整數轉換以及Hadamard正逆整數轉換,並整合三者運算中的共同性,共享硬體,進而及硬體成本的效果。而在量化部份,採用CSD(Cannonic Signed Digit)乘法器取代傳統乘法器以節省乘法器硬體面積,並利用乘法樹(adder tree)的方式提升處理速度。最後換算本系統處理HDTV(1920x1080@30Hz)所需的時間,在1秒的期間內,僅需7.7%的時間即可完成整數轉換與量化的運算,還有剩餘92%的時間可以讓H.264/AVC中其他的功能區塊使用,因此可即時編碼處理HDTV影像。

The H.264/AVC is the newest video coding standard. The video coding progress in the H.264 gets better compressing rate and video quality than the previous standards. The H.264/AVC can meet the applications of HDTV or DVD easily. However, the utilization of the H.264/AVC comes at a cost in considerably increased complexity at the encoder, and then it will increase the difficulty in hardware implementations.
In the thesis, we focus on the transforms and quantization of the H.264 and we also realize the hardware. In the transforms of the H.264, we include the 4x4 forward/inverse integer DCT, the 8x8 forward/inverse integer DCT, and the Hadamard forward/inverse transforms.
We integrate the same parts of the three transforms to reduce the hardware area and the cost. For the quantization, we use the CSD (canonic signed digit) multiplier hardware architecture instead of the traditional multiplier hardware architecture to reduce the hardware area. Then we use adder tree to improve the hardware performance of the quantization. Finally, we can use the proposed hardware design to handle the video coding with the HDTV(1920x1080@30Hz) video format, and the proposed hardware just needs only 7.7% work time for the transforms and quantization. Then we have 92% rest time to support the other functions of the H.264/AVC. Thus, the proposed architecture has the capability to achieve the real-time processing of HDTV video coding.
URI: http://hdl.handle.net/11455/7442
其他識別: U0005-1007200713245000
Appears in Collections:電機工程學系所

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