Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/7496
標題: 摺疊內插式類比數位轉換器之實現
Implementation of Folding and Interpolating Analog-to-Digital Converter
作者: 李明謙
關鍵字: folding;摺疊;interpolating;analog-to-digital converter;內插;類比數位轉換器
出版社: 電機工程學系
摘要: 
摘要
由於近年來CMOS製程的進步,使得在同一塊晶片上可整合更多的數位訊號處理系統,在許多的應用上,例如:高畫質數位電視、視訊系統、通訊系統、醫療影像系統….等,對於類比數位轉換器都有著快速度、高解析的要求,本論文中利用摺疊內插式的架構設計一個10位元、取樣頻率超過50MHz以上的類比數位轉換器,在這裡我們利用了分佈式的前置增益級和平均的技巧以減少非線性的影響,而且在於功率消耗、取樣頻率、以及晶片面積大小上取得適當的平衡。這次摺疊內插式類比數位轉換器的實現是利用台積電0.35μm 、1p4m 、 CMOS製程來完成,根據模擬結果顯示,在輸入一2 MHz的弦波且取樣頻率為66MHz可得59dB 的訊號雜訊比,相當於9.6-bit的有效位元。電路的最大差動非線性誤差與積分非線性誤差各為0.3LSB和0.5LSB,電路操作在66MHz的取樣頻率下,功率消耗為200mW.

ABSTRACT
In recent years, due to the evolution of CMOS technology, it is possible to integrate more and more digital signal processing system on a single chip. Today's specifications for high-speed, high-resolution analog-to-digital converters are determined by the applications such as HDTV, video, communication, and medical imaging systems. This thesis describes the design of a 10-bit, CMOS analog-to-digital converter, which can operate at over 50 MSample/s, and is based on a cascaded folding and interpolating architecture. The ADC utilizes the distributed-gain preamplifiers and the averaging technique to improve differential non-linearity (DNL). This folding and interpolating converter architecture realizes an appropriate balance between power dissipation, clock frequency, and chip size. The folding and interpolating A/D converter is fabricated in a TSMC 0.35-μm CMOS technology. The converter achieves differential and integral non-linearity of 0.3 and 0.5 LSB, and a signal-to-(noise + distortion) ratio of 59 dB with a 2 MHz sinusoidal input, which is equal to 9.6 effective bits, at a sampling rate of 66 MHz. The ADC dissipates 200 mW from a 3.3V supply and occupies an area of 1.3 1.4 mm2.
URI: http://hdl.handle.net/11455/7496
Appears in Collections:電機工程學系所

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