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標題: 基於記憶體的IP路由表之硬體設計
Hardware Design of a RAM-based IP Routing Table
作者: 林明發
Lim, Beng-Huat
關鍵字: routing table lookup;路徑查尋;IP routing;IPv4;IPv6;hardware pipeline;multi-gigabit;RAM-based;IP 路徑;路由表;硬體管線;數十億位元;基於記憶體
出版社: 電機工程學系
在路由器的設計上,IP路徑的查尋無疑地將是其中一個最困難設計的部份。今天,因為網路流量的急速增加,尤其是當網路速率達到每秒數十億位元時, IP路徑的查尋速度已成為路由器本身的瓶頸。因此,我們在這裡提出了一種查尋方法可以快速而且有效地進行IP路徑的新增、刪除機制,而且不會降低整體的查尋速度。在妥善管理記憶體的配置及閒置情況,以及使用創新的模組內部跳躍機制之下,此方法所需的記憶體空間成功地被減少了。在此,我們使用硬體描述語言進行此方法的硬體設計,並且在硬體管線方式下於每次的記憶體存取後即有查尋結果的輸出。模擬結果顯示,此架構只需要約0.59Mbytes的記憶體即可以在每秒內完成三十百萬個查尋動作,因而其可以支援達三百億位元的網路連結速率。而且最重要的是,此架構甚至可以按比例放大以支援未來的IPv6位址。

One of the pertinent issues in IP router design is the IP routing table lookup. Today, with high-speed multi-gigabit links required in the Internet, the lookup becomes a great bottleneck. In this paper, we propose a lookup scheme that can efficiently handle IP routing lookup, insertion, and deletion inside the routing table. This method is less complex in comparison to the other schemes. An efficient memory management method is used to decrease the memory usage in our design. In addition, a novel skip function is introduced to further decrease the memory size. Hardware design of the routing table was carried out using the Verilog hardware description language. It can achieve one route lookup for every memory access using the hardware pipeline implementation. Timemill post-layout simulation results show that the chip can furnish approximately 30x10^6 lookups/s, and thus it can support up to 30 gigabits per second link speed. Furthermore, only a small memory size of 0.59 Mbytes is needed in the design and it can also be easily scaled from IPv4 to IPv6 in the future.
Appears in Collections:電機工程學系所

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