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標題: 高速全數位鎖相迴路
High Speed All Digital Phase-Locked Loop
作者: 游榮豪
You, Rung-Hau
關鍵字: 全數位鎖相迴路;ADPLL;鎖相迴路;延遲鎖相迴路;相頻偵測器;PLL;All Digital Phase-Locked Loop;Phase-Locked Loop;DLL;Delay-Locked Loop;PFD;Phase-Frequency Detector
出版社: 電機工程學系
本篇論文描述一個高速全數位鎖相迴路的架構與設計,使用取樣編碼方式,能在四個參考週期內決定DCO操作模式及輸入信號在十六組頻率區段中的位置並局部修改演算流程與DCO設計,使本電路具有較快的搜尋速度、較短的鎖定時間、較小的Phase Jitter,並可操作在極高的頻率。架構中可分為數位控制振盪器,頻率偵測器、相位偵測器、UP/DN Counter、控制單元、啟動電路、取樣電路、編碼電路、位元指標器、除頻器及相位選擇器等十一個部分。操作程序可分為頻率獲取、相位獲取、頻率維持及相位維持四種程序,利用控制單元執行二元搜尋演算法(Binary Search)改變UP/DN Counter增益,控制DCO輸出,使ADPLL輸出與參考信號一致完成鎖相程序。
模擬結果顯示當DCO分別操作在1.25GHz與2.5GHz時相位差(Phase Error)皆可小於100ps,系統dead zone小於30ps,所需鎖定時間少於34個參考時脈週期(演算法)或1us(實際模擬),鎖定範圍在DCO模式0時為2.3GHz ~ 2.6GHz,模式1時為0.8GHz ~ 1.3GHz,使用製程是TSMC 1P4M 0.35um,操作電壓3V。功率消耗在1.25GHz時為106.1mW,與2.5GHz時為91.46mW。

This thesis describes the architecture and design of a high speed all digital phase-locked loop (ADPLL), which uses sample and encode method to decide DCO operation model and frequency region of the input signal in 16 levels. The method can also modify part of algorithm and DCO design. The proposed ADPLL design has characteristics of fast search speed, short frequency locking time, small phase jitter and high operating frequency. This architecture comprises digital controlled oscillator (DCO), frequency detector (FD), phase detector (PD), UP/DN counter, control unit, start circuit, sample circuit, encoder, bit indicator, divider, phase chooser. The phase-lock procedures for this proposed ADPLL are frequency acquisition, phase acquisition, frequency maintenance and phase maintenance. The phase-lock procedures control unit to execute binary search algorithm, which changes UP/DN counter gain and controls the DCO output. When the ADPLL output is in phase with reference clock the phase-lock procedures are accomplished.
The proposed ADPLL is simulated and implemented by the TSMC 0.35μm 1P4M technology. The supply voltage is 3V. The simulation results show that when DCO operates at 1.25GHz or 2.5GHz, the phase error is smaller than 100ps. The system dead zone is smaller than 30ps, and the lock in time is smaller than 34 reference clock cycles (algorithm) or 1us (simulation). The lock-in range is 2.3GHz to 2.6GHz in the mode 0 and 0.8GHz to 1.3GHz in the mode 1. The power consumption is 106.1mW at 1.25GHz and 91.46mW at 2.5GHz.
Appears in Collections:電機工程學系所

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