Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/7537
標題: 低電壓CMOS電流模式取樣保持電路的設計
Design of Low-Voltage Current-Mode CMOS Sample-and-Hold Circuits
作者: 陳天賜
T.S.Chen
關鍵字: Low-Voltage;低電壓;Current-Mode;Sample-and-Hold;Current-Mirror;Voltage-to-Current;FFT;SNR;ENOB;電流模式;取樣保持;電流鏡;電壓到電流;快速傅立葉轉換;信號雜訊比;解析度
出版社: 電機工程學系
摘要: 
摘 要
本篇論文設計了一個低電壓、電流模式的CMOS取樣保持電路。
提出的電路中包括一對電流鏡電路及低電壓運算放大器,利用運算放大器虛短路的特性,使得在輸入端點的電位可以獨立於輸入信號而維持定值;這樣,輸入信號只要經一個外接電阻和電容串聯組成的電路,便能將輸入為電壓形式的信號轉換成對應的電流形式。其中低電壓運算放大器是由兩個串接的共源極放大器(由MOS電晶體和定電流源組成)來實現的,這種架構可以很輕易地使輸入端點的電壓維持在電源電壓的中點。另外,整個電路只用了兩個互補式電晶體對的開關,並配置成差動組態,它能將開關電晶體引起的穿越效應所造成的誤差降到最小。
所提出的電路是採用TSMC 0.35μm CMOS 1P4M的製程來設計並以Hspice來模擬;結果顯示這個電路操作在1.5V的單一電源下可以達到10位元的解析度、±200μA的輸入信號範圍、小於0.07% 的非線性、在50MHz取樣頻率下的輸入信號頻率為1-MHz和8-MHz時的信號雜訊比分別是58dB和56dB、低於1.7mW的功率消耗及70μm×70μm 的晶片Layout面積。

Abstract
The low-voltage, current-mode, CMOS, sample-and-hold circuit has been designed in this thesis. The proposed circuit includes a pair of current-mirror circuits with low-voltage operational amplifier, which keeps the input node voltage constant and independent of the input signal. Thus, conversion of the input voltage signal to current form that can be done by simply connecting an external resistor and capacitor. The low-voltage operational amplifier is implemented with a cascade MOS transistor and a constant current source in a common-source amplifier configuration, which can easily maintain the input node voltage of the circuit at half of the supply voltage. The proposed circuit uses only two complementary switching transistors in differential form so that the feed-through error caused by the switching transistor is minimized.
The sample-and-hold circuit is designed using the TSMC 0.35μm CMOS 1P4M technology and simulated by Hspice. The simulation results show that the circuit can achieve 10-bit resolution under a single supply voltage of 1.5V. The input signal range is ±200μA. Its nonlinearity is below 0.07%. The signal-to-noise (SNR) is 58 dB and 56dB with 1-MHz and 8-MHz input signal at 50 MHz sampling rates. The power consumption is less than 1.7mW. The area of layout is 70μm×70μm.
URI: http://hdl.handle.net/11455/7537
Appears in Collections:電機工程學系所

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