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標題: 低電壓CMOS電流模式取樣保持電路的設計
Design of Low-Voltage Current-Mode CMOS Sample-and-Hold Circuits
作者: 陳天賜
關鍵字: Low-Voltage;低電壓;Current-Mode;Sample-and-Hold;Current-Mirror;Voltage-to-Current;FFT;SNR;ENOB;電流模式;取樣保持;電流鏡;電壓到電流;快速傅立葉轉換;信號雜訊比;解析度
出版社: 電機工程學系
摘 要
所提出的電路是採用TSMC 0.35μm CMOS 1P4M的製程來設計並以Hspice來模擬;結果顯示這個電路操作在1.5V的單一電源下可以達到10位元的解析度、±200μA的輸入信號範圍、小於0.07% 的非線性、在50MHz取樣頻率下的輸入信號頻率為1-MHz和8-MHz時的信號雜訊比分別是58dB和56dB、低於1.7mW的功率消耗及70μm×70μm 的晶片Layout面積。

The low-voltage, current-mode, CMOS, sample-and-hold circuit has been designed in this thesis. The proposed circuit includes a pair of current-mirror circuits with low-voltage operational amplifier, which keeps the input node voltage constant and independent of the input signal. Thus, conversion of the input voltage signal to current form that can be done by simply connecting an external resistor and capacitor. The low-voltage operational amplifier is implemented with a cascade MOS transistor and a constant current source in a common-source amplifier configuration, which can easily maintain the input node voltage of the circuit at half of the supply voltage. The proposed circuit uses only two complementary switching transistors in differential form so that the feed-through error caused by the switching transistor is minimized.
The sample-and-hold circuit is designed using the TSMC 0.35μm CMOS 1P4M technology and simulated by Hspice. The simulation results show that the circuit can achieve 10-bit resolution under a single supply voltage of 1.5V. The input signal range is ±200μA. Its nonlinearity is below 0.07%. The signal-to-noise (SNR) is 58 dB and 56dB with 1-MHz and 8-MHz input signal at 50 MHz sampling rates. The power consumption is less than 1.7mW. The area of layout is 70μm×70μm.
Appears in Collections:電機工程學系所

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