Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/7547
標題: 非晶矽薄膜電晶體在閘極與汲極交流訊號偏壓下之可靠度研究
Study on the Reliability of Hydrogenated Amorphous Silicon Thin Film Transistors under AC Gate and Drain Bias Stress
作者: 楊中維
Yang, Chung-Wei
關鍵字: a-Si:H TFT;非晶矽薄膜電晶體;Reliability;AC bias stress;DC bias stress;可靠度;交流偏壓;直流偏壓
出版社: 電機工程學系所
引用: [1] Y. Byun, D. Beer, M. Yang, T. Gu, “A novel amorphous silicon thin film transistor for AMLCDs,” Device Research Conference, 1995. Digest. 1995 53rd Annual, pp.160-161, 1995. [2] Y. Hishikawa, K. Watanabe, S. Tsuda, M. Ohnishi, and Y. Kuwano, “Raman Study on Silicon Network of Hydrogenated Amorphous Silicon Film Deposited by a Glow Discharge,” Jpn. J. Appl. Phys. vol.24, no.5, pp. 385-389, 1985. [3] R. A. Street and M. J. Thompson, “Electronic States at the Hydrogenated Amorphous Silicon/Silicon Nitride Interface,” Appl. Phys. Lett, vol.45, pp.769-771, 1984. [4] K. Hiranaka, T. Yoshimura, and T. Yamaguchi, “Effect of the Deposition Sequence on Amorphous Silicon Thin Film Transistors,” Jpn. J. Appl. Phys. 28, no.11, pp.2197-2200, 1989. [5] H. Uchida, K. Takechi, S. Nishida and S. Kaneko, “High-Mobility and High-Stability a-Si:H Thin Film Transistors With Smooth SiNx/a-Si Interface,” Jpn. J. Appl. Phys. 30, pp.3691-3694, 1991. [6] L. L. Kazmerski, “Polycrystalline and Amorphous Silicon Thin Film and Devices,” Academic Press, 1980. [7] D. L. Staebler and C. R. Wronski, “Optically induced conductivity changes in discharge-produced hydrogenated amorphous silicon,” J. Appl. Phys. 51, pp.3262-3268, 1980. [8] M. Stutzmann, W. B. Jackson, and C. C. Tsai, “Kinetics of the Staebler-Wronski effect in hydrogenated amorphous silicon,” Appl. Phys. Lett.45(10), vol.15, pp.1075-1077, 1984. [9] B. Pivac, I. Kovacevic, I. Zulim, V. Gradisnik, “Effect of Light Soaking on Amorphous Silicon,” IEEE, pp.884-887, 2000. [10] M. J. Powell, “The Physics of Amorphous-Silicon Thin-Film Transistors,” IEEE trans. Electron Devices, vol.36, no.12, pp.2753-2763, 1989. [11] C. Y. Huang, T. H. Teng, “The Instability Mechanisms of Hydrogenated Amorphous Silicon Thin Film Transistors under AC Bias Stress,” Jpn. J. Appl. Phys. Vol.39, pp.3867-3871, 2000. [12] K. S. Karim, A. Nathan, M. Hack, and W. I. Milne, “Drain-Bias Dependence of Threshold Voltage Stability of Amorphous Silicon TFTs,” IEEE trans. Electron Devices, vol.25, No.4, pp.188-190, 2004. [13] M. J. Powell, C. V. Berkel, “Bias dependence of instability mechanisms in amorphous silicon thin-film transistors,” Appl. Phys. Lett. 51(16), pp.1242-1244, 1987. [14] C. Y. Huang, J. W. Tsai, T. H. Teng, C. J. Yang, and H. C. Cheng, “Turnaround Phenomenon of Threshold Voltage Shifts in Amorphous Silicon Thin Film Transistors under Negative Bias Stress,” Jpn. J. Appl. Phys. vol.39, no.10, pp.5763-5766, 2000. [15] H. C. Cheng, C. Y. Huang, J. W. Lin and J. J. H. Kung, “The reliability of amorphous silicon thin film transistors for LCD under DC and AC stresses,” Solid-State and Integrated Circuit Technology, 1998. Proceedings. 1998 5th International Conference on 21-23 Oct. pp.834-837, 1998. [16] C. Y. Huang, T. H. Teng, J. W. Tsai, and H. C. Cheng, “The Instability Mechanism of Hydrogenated Amorphous Silicon Thin Film Transistors under AC Bias Stress,” Jpn. J. Appl. Phys. vol.39, no.7A, pp.3867-3871, 2000. [17] B. C. Lim, Y. J. Chio, J. H. Choi and J. Jang, “Hydrogenated Amorphous Silicon Thin Film Transistor Fabricated on Plasma Treated Silicon Nitride,” IEEE trans. Electron Devices, vol.47, No.2, pp.367-371, 2000. [18] C. Y. Wu, C. H. Chen, Y. C. Kuan, and K. S. Sun,“High Stable a-Si:H TFTs Prepared with Optimum SiNx Films by PECVD Using Taguchi Method,” IDW, pp.1085-1088, 2005. [19] F. S. Wang, M. J. Tsai, and H. C. Chang, “The Effect of NH3 Plasma Passivation on Polysilicon Thin-Film Transistors,” IEEE Electron Device Lett, vol.16, pp.503-505, 1995. [20] S. W. Lee, K. S. Cho, B. K. Choo, and J. Jang, Member, “Copper Gate Hydrogenated Amorphous Silicon TFT With Thin Buffer layer,” IEEE Electron Device Lett, vol.23, No.6, pp.324-326, 2002. [21] J. H. Choi, C. S. Kim, B. C. Lim, and J. Jang, “A Novel Thin Film Transistor Using Double Amorphous Silicon Active Layer,” IEEE trans. Electron Devices, vol.45, No.9, pp.2074-2076, 1998. [22] D. B. Thomasson and T. N. Jackson, “High Mobility Tri-Layer a-Si:H Thin-Film Transistors with Ultrathin Active Layer,” IEEE Electron Device Lett, vol.18, No.8, pp.397-399, 1997. [23] J. B. Choi, D. C. Yun, Y. I. Park, J. H. Kim, “Properties of hydrogenated amorphous silicon thin film transistors fabricated at 150℃,” Journal of Non-Crystalline Solids 266-269, pp.1315-1319. 2000. [24] J. L. Lin, W. J. Sah, and S. C. Lee, “Amorphous-Silicon Thin-Film Transistors with Very High Field-Effect Mobility,” IEEE Electron Device Lett, vol.12, No.3, pp.120-121, 1991.
摘要: 
在本論文中,我們使用完成三道光罩之非對稱式非晶矽薄膜電晶體做可靠度測試,找出電晶體在直流與交流電壓操作下之不穩定性並深入的探討。而本論文有兩大主軸:(1)電晶體給予偏壓應力的可靠度測試、(2)NH3電漿處理後,給予偏壓應力的可靠度測試。

(1)電晶體偏壓應力測試:先在閘極上給予直流正、負偏壓與交流正、負偏壓應力測試,可發現非晶矽薄膜電晶體在直流正、負偏壓時,電性皆有最大的影響。而在交流正偏壓下,電晶體特性並不受頻率的影響,在交流負偏壓下,電晶體特性則受頻率的影響。主要原因是我們對於電晶體閘極施予負偏壓時,是吸引電洞至閘極介電層,而如果負偏壓頻率過高,則沒有足夠的電洞來跟隨脈波起伏而有所反應。因為實際面板在運作時就是閘極與汲極採用交流方式操作,所以接著探討在閘極上與汲極上給予直流正、負偏壓與交流正、負偏壓應力測試,來比較非晶矽薄膜電晶體在閘極與汲極分別有偏壓下,電晶體的最大衰退變化量,再加上閘極與汲極給予非同步偏壓的狀況,探討此一非同步狀況對於電晶體的影響,以及了解是哪些機制造成如此差異。

(2)NH3電漿處理:我們先找出NH3電漿處理的最佳射頻條件,由先前做的偏壓測試結果,分別找出直流與交流偏壓下,對電晶體特性影響最大的偏壓條件,利用此條件來對已做完電漿處理的電晶體做偏壓應力測試,可發現電漿處理完後的電晶體對於偏壓應力的測試,在電性上皆有明顯的改善。

In this paper, we investigate the reliability of asymmetric a-Si:H TFTs with three mask process. And we study the instability mechanisms of a-Si:H TFTs under alternating current (AC) and direct current (DC) bias stress. This thesis can be divided into two major parts: (1) study on the reliability of TFTs under the various bias stress, and (2) the reliability of TFTs with and without NH3 plasma treatment under the bias stress.

(1) TFTs under bias stress: we use positive, negative DC and AC bias stress on the gate electrode. We can observe that TFTs under the DC bias stress has the maximum effect for electrical characteristic. Under positive AC bias stress, the degradation characteristic of TFTs is independent of frequency. However, under negative AC bias stress, the degradation characteristic of TFTs depends on frequency. The reason is that when negative AC gate bias stress on the TFTs, the holes would be attracted to the gate interface. There are no sufficient holes to follow the negative AC bias stress when high frequency is chosen. Due to the operation of the flat panel displays is under AC signal, therefore we discuss the degradation under DC and AC bias stress which include positive and negative bias stress on gate and drain of TFTs. What's more, we discuss asynchronous gate and drain bias stress on TFTs, and study the degradation mechanisms.

(2) NH3 Plasma treatment: First, we find out the best RF power of NH3 plasma treatment. Then we apply the most serious bias stress conditions which are found in the former part to the TFTs with NH3 plasma treatment. Finally, we compare the TFTs with and without NH3 plasma treatment, and we find the former has the significant improvement after bias stress.
URI: http://hdl.handle.net/11455/7547
其他識別: U0005-1708200700351000
Appears in Collections:電機工程學系所

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