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標題: P型通道複晶矽薄膜電晶體之可靠度研究
Study on the Reliability of P Channel Poly-Silicon Thin Film Transistors
作者: 張為鈞
Chang, Wei-Chun
關鍵字: Poly-silicon;複晶矽;TFTs;Reliability;BTS;AC bias stress;薄膜電晶體;可靠度;偏壓溫度應力;交流偏壓應力
出版社: 電機工程學系所
引用: Chapter 1 [1.1] “下世代液晶顯示器中之關健技術, ”林敬偉、鄭晃忠,電子月刊第六卷第十一期, ”低溫複晶矽薄膜電晶體技術“ [1.2] H. Kuriyama et al., “ An asymmetric memory cell using a C-TFT for ULSI SRAM,” Symp. On VLSI Tech., p.38, (1992) [1.3] T. Yamanaka, T. Hashimoto, N. Hasegawa, T. Tanala, N. Hashimoto, A Shimizu,N. Ohki, K. Ishibashi, K. Sasaki, T. Nishida, T. Mine, E. Takeda, and T. Nagano,“Advanced TFT SRAM cell technology using a phase-shift lithography,” IEEETrans. Electron Devices, Vol. 42, pp.1305-1313, (1995) [1.4] Young, N.D.; Harkin, G.; Bunn, R.M.; McCulloch, D.J.; French, I.D., “The fabrication and characterization of EEPROM arrays on glass using a low-temperature poly-Si TFT process,” IEEE Electron Devices, Volume43, Issue 11, pp. 1930 – 1936, Nov. (1999) [1.5] Yamauchi,N.; Inaba , Y.; Okamura , M, “ An integrated Photodetector- amplifier using a-Si p-i-n photodiodes and poly-Sithin-film transistors, ” IEEE Photonics Technology Letters, Volume 5, Issue 3, pp. 319– 321, (1993) [1.6] Hayashi, Y.; Hayashi, H.; Neyishi, M.; Matsushita, T.; Yagino, M.; Endo, T., “A Thermal Printer Head with CMOS Thin-film Transistors and Heating Elements Integrated on a Chip,” Solid-State Circuits Conference, 1988. Digest of Technical Papers. ISSCC. 1988 IEEE International, pp. 266-267, 400-401, February, (1988) [1.7] Young, N.D.; Harkin, G.; Bunn, R.M.; McCulloch, D.J.; Wilks, R.W.; Knapp, A.G, “Novel fingerprint scanning arrays using polysilicon TFT''s on glass And polymer substrates,” IEEE, Electron Device Letters, Volume 18, Issue 1, pp. 19 – 20, (1997) [1.8] H. J. Kim and J. S. Im, “New excimer-laser-crystallization method for producing large-grained and grain boundary-location-controlled Si films for thin film transistors,” Appl. Phys. Lett., vol.68, pp.1513-1515, (1996) [1.9] M. Cao, S. Talwar, K. Josef Kramer, T. W. Sigmon, and K. C. Saraswat, “A high-performance polysilicon thin-film transistor using XeCl excimer laser crystallization of pre-patterned amorphous Si films,” IEEE Trans. Electron Devices, vol. 43, pp561-567,(1996) [1.10] J. H. Jeon, M. C. Lee, K. C. Park, and M. K. Han, “A new polycrystallines silicon TFT with a single grain boundary in the channel,” IEEE Electron Device Lett., vol. 22,pp.429-431, (2001) [1.11] S. Uchikoga and N. Ibaraki, “Low temperature poly-Si TFT-LCD by excimer laser anneal,” Thin Solid Films, vol. 383, pp.19-24, (2001) [1.12] “元件可靠度, ”鄭敦仁,電子與材料第八期 Chapter 2 [2.1] K.Kiahara, Y. Ohashi, and Y. Katoh, “Submicron-scale characterization of poly-Si thin films crystallized by excimer laser and continuous-wace laser,” Journal of applied physics, Volume 95, Number 12, (2004) [2.2] Y. Uraoka, Y.Mprita, H. Yano, T. Hatayama, and T. Fuyuki, “Gate length dependence of hot carrier reliability in low-temperature polycrystalline-silicon p-channel thin film transistors,” Jpn. J. App. Phys. Vol. 41, pp. 5894-5899, (2002) [2.3] Ching-Wei Lin, Chang-Ho Tseng, Ting-Kuo Chang, Yuan-Hsun Chang, Fang-Tsun Chu, Chiung-Wei Lin, Wen-Tung Wang and Huang-Chung Cheng, “An investigation of bias temperature instability in hydrogenated low-temperature polycrystalline silicon thin film transistors,” Jpn. J. App. Phys. Vol. 41, pp. 5517-5522, (2002) [2.4] Nikolaos A. Hastas, Charalabos A. Dimitriadis, Jean Brini, and George Kamarinos, “hot-carrier-induced degradation in short p-channel nonhydrogenated polysilicon thin-film transistors,” IEEE transactions on electron devices, Vol.49, No. 9, (2002) [2.5] Kook Chul Moon, Jae-Hoon Lee, and Min-Koo Han, “The study of hot-carrier stress on poly-Si TFT employing C-V measurement,” IEEE transactions on electron devices, Vol. 52, No. 4, (2005) [2.6] Yukiharu Uraoka, Hiroshi Yano, Tomoaki Hatayama and Takashi Fuyuki, “Hor-carrier effect in low-temperature poly-Si p-ch thin-film transistors under dynamic stress,” Jpn. J. App. Phys. Vol. 41, pp. L13-L16, (2002) [2.7] Ya-Hsiang Tai, Shih-Che Huang, and Chien-Kwen Chen, “Analysis of poly-Si TFT degradation under gate pulse stress using the slicing model,” IEEE transactions on electron devices, Vol. 27, No. 12, (2006)



Poly-Si TFTs has been widely used recently, and nowadays, the reliability of TFTs plays an important role. When poly-Si TFTs are applied to the flat panel displays, the TFTs is driven by AC signal. Therefore, the reliability test is not only focus on DC bias stress, the instability of TFTs under AC stress also becomes important now. In this thesis, we study the reliability of the p-channel TFTs by (1) bias temperature stress (BTS), and (2) alternating current (AC) bias stress.

For BTS, we use TFTs with three different channel lengths to realize the BTS. We apply a hot chuck to control the temperature and constant voltage on the gate and drain. We find that the shorter the channel length is, the more serious degradation will occur; and we also observe that the TFTs with the same channel length, the higher temperature we apply, the larger damage on TFTs will occur. In addition, the “turn-over” behavior will appear in the degradation of electrical characteristic, and it depends on the channel length and the temperature we apply. Besides I-V measurement, we also measure the C-V characteristics. We discover that after BTS, the location of degradation is mainly near the source end of TFTs.

For AC stress, we use TFTs with the same dimension, and we apply synchronous and asynchronous AC gate signal and drain signal. Under synchronous AC gate and drain bias stress, the lower frequency of AC signal will cause a more serious degradation. And under asynchronous AC gate and drain bias stress, we choose a specific frequency that would cause the largest damage on TFTs from above experiments. We find that under not only drain signal delay stress but also gate signal delay stress, the larger delay portions will cause the larger damage on TFTs
其他識別: U0005-1708200711045200
Appears in Collections:電機工程學系所

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