Please use this identifier to cite or link to this item: http://hdl.handle.net/11455/7561
DC FieldValueLanguage
dc.contributor楊榮吉zh_TW
dc.contributor林維亮zh_TW
dc.contributor.advisor楊清淵zh_TW
dc.contributor.author凃嘉杰zh_TW
dc.contributor.authorTu, Chia-Chiehen_US
dc.contributor.other中興大學zh_TW
dc.date2008zh_TW
dc.date.accessioned2014-06-06T06:40:13Z-
dc.date.available2014-06-06T06:40:13Z-
dc.identifierU0005-2008200714462400zh_TW
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dc.identifier.urihttp://hdl.handle.net/11455/7561-
dc.description.abstract本論文主要探討高頻高效能的壓控振盪器,與應用鎖相迴路技術實現直接除小數的頻率合成器,主要可分成三部分。第一部分先介紹振盪器的概念、振盪原理,以及內部的元件和相位雜訊的定義;此外,比較數個基本型電感-電容式的振盪器,最後介紹四相位輸出的電感-電容式壓控振盪器。 在本論文第二部分中將利用積體化變壓器的架構實現可調電感的技術並應用於壓控振盪器中,並對其進行分析。本電路架構以TSMC 0.18uM CMOS 製程實現。中心頻率操作於6.42GHz,可調頻率範圍約為600MHz,在1MHz偏移處相位雜訊約為-122.85dBc/Hz,總功率消耗為28mW。 第三部分主要介紹以電感-電容式振盪器的概念實現高頻高效能的壓控振盪器;其中包括二個注入鎖定式四相位壓控振盪器架構和一個電感式耦合分配振盪器。其中,電感式耦合分配振盪器改善了以往利用被動元件-電感,產生四相位的缺點-閃爍雜訊,而利用被動元件-電感,產生四相位。而注入鎖定式振盪器的部分,主要以高頻的壓控振盪器利用注入鎖定的原理結合第一級預除器,並產生四相位輸出。此三個電路架構皆以TSMC 0.18 製程實現,輸出頻率約為9-10GHz。 最後一部分將利用前面提到的注入鎖定式振盪器架構實現一高頻的直接除小數頻率合成器。本頻率合成器以TSMC 0.13 uM RF CMOS製程實現,輸出頻率為20.2GHz,參考頻率為157MHz,除率為128.5,總消耗功率為68mW,總面積為1.13*1.6mm2。zh_TW
dc.description.abstractThis thesis mainly describes a direct fractional-N frequency synthesizer with a phase-lock-loop technique by using high-frequency and high-performance oscillators. The thesis could be divided into four parts. The first part is about oscillator fundamentals, inner devices and the definition of phase noise. Furthermore, we also compare several basic LC oscillators, and quadrature( four-phase ) oscillator design is described. The second part of this thesis introduce the integrated transformer to achieve inductance-tuning technique in LC-oscillators. The transformer based VCO topology is fabricated in TSMC 0.18 uM CMOS technology. The center frequency is at 6.42GHz, and frequency tuning range is about 600MHz. The phase noise at 1MHz is about -122.85dBc/Hz. The total power consumption is 28mW. The third part mainly introduces high-frequency and high-performance oscillators based on LC-VCOs. There are two injection-locked quadrature- VCOs (QVCO) and an inductor-coupled distributed oscillator which could also generate quadrature signals. The distributed oscillator uses passive components-inductors for enforcing signal coupling, instead of active components-MOSFETs for eliminating flicker noise from active components. The injection-locked oscillator contains a high-frequency VCO and a prescaler. Based on injection-locked theory, the output frequency of prescaler will be locked by a multiple frequency of VCO and generate quadrature signals. The three topology are fabricated in TSMC 0.18 technology, and output frequencies range from 9 to 10GHz. In the last part, we achieve a high-frequency fractional-N frequency synthesizer by mainly using a VCO and an injection-locked frequency divider. The frequency synthesizer is fabricated in TSMC 0.13 uM RF CMOS technology. Its output frequency is at about 20.2GHz, and its reference frequency is about 157MHz. The division ratio is 128.5, the total power consumption is 68mW, and the total area is 1.13*1.6mm2.en_US
dc.description.tableofcontentsTable of Contents 誌謝- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - i 摘要(中文) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ii 摘要(英文) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- iii Table of Contents - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -iv Chapter 1 Introduction 1.1 Motivation - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1.2 Overview of Thesis - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 Chapter 2 Oscillator Fundamentals 2.1 Oscillation Thesis - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 3 2.2 LC Oscillators - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 5 2.2.1 Cross-coupled Oscillators - - - - - - - - - - - - - - - - - - - - - - 9 2.2.2 Monolithic Varactors - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 11 2.2.3 Phase Noise - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 14 2.3 Differential LC VCOs - - - - - - - - - - - - - - - - - - - - - - - - 15 2.4 Quadrature Oscillators - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 16 2.4.1 In-Phase Coupling - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 19 2.4.2 Anti-Phase Coupling - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -21 Chapter 3 Integrated Transformer-Based VCO 3.1 Integrated and Inductor-Transformers- - - - - - - - - - - - - - - - - - - - - - 25 3.2 Integrated Transformer-Based VCO- - - - - - - - - - - - - - - - - - - - - - - 28 3.2.1 Analysis of Transformer Characteristic - - - - - - - - - - - - - - - - - - 28 3.2.2 Circuit Description- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 31 3.2.3 Measurements- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 32 3.3 Conclusion and Discussion- - - - - - - - - - - - - - - - - - - - - - - - - - - - - -36 Chapter 4 High Frequency Quadrature Voltage-Controlled-Oscillators 4.1 Injection-Locked Frequency Divider - - - - - - - - - - - - - - - - - 37 4.2 Direct Injection-Locked QVCO - - - - - - - - - - - - - - - - - - - - - 39 4.2.1 Circuit Description and Simulation - - - - - - - - - - - - - - - - - - - - -39 4.2.2 Measurements - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 41 4.2.3 Discussion - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -43 4.3 Low-Phase Noise Distributed QVCO - - - - - - - - - - - - - - - - - - - - - - 45 4.3.1 Circuit description - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 45 4.3.2 Thesis Analysis - - - - - - - - - - - - - - - - - - - - - - - - - - - - 47 4.3.2.1 Distributed Oscillator - - - - - - - - - - - - - - - - - - - - - - - - - 47 4.3.2.2 Transformer- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 49 4.3.2.3 Single-Sideband-Mixer- - - - - - - - - - - - - - - - - - - - - - - - - - 50 4.3.3 Circuit Simulation - - - - - - - - - - - - - - - - - - - - - - - - - - 51 4.3.4 Measurements - - - - - - - - - - - - - - - - - - - - - - - - - - 53 4.3.5 Discussion - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 55 Chapter 5 A Fractional-N Frequency Synthesizer with a High-Frequency VCO 5.1 Synthesizer Architecture - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 58 5.2 Circuit Descriptions- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 59 5.2.1 Phase and Frequency Detector- - - - - - - - - - - - - - - - - - - - - - - - 59 5.2.2 Charge Pump - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 61 5.2.3 Loop Filter - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 62 5.2.4 Voltage-Controlled Oscillator and Miller Divider - - - - - - - - - - - 65 5.2.5 Phase-Selection Circuit - - - - - - - - - - - - - - - - - - - - - - - - - - - - 66 5.3 Circuit Simulation - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 66 5.4 Measurement Consideration - - - - - - - - - - - - - - - - - - - - - - - - - - - - 71 5.5 Discussion - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 71 Chapter 6 Conclusion and Future Work Conclusion and Future Work - - - - - - - - - - - - - - - - - - - - - - - - - - - - 73 Reference Books References- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 74 Appendix ◎ Measure Environment - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -78 ◎ Chia-Chieh Tu and Ching-Yuan Yang, ” A 6.5-GHz LC VCO with Integrated-Transformer Tuning,” in Proc. IEEE Asia Pacific Conf. (APCCAS), pp. 510 – 513, Dec. 2006. - - - - - - - - - - - - - - - - - - - - - - - -80 List of Tables Table.3.1 VCO performance summary - - - - - - - - - - - - - - - - - - - - - - - - - - 35 Table.3.2 VCOs summary - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 35 Table.4.1 DO performance summary - - - - - - - - - - - - - - - - - - - - - - - - - - - 54 Table.4.2 VCOs performance summary - - - - - - - - - - - - - - - - - - - - - - - - - 55 Table.4.3 Phase noise comparison by different bias circuits - - - - - - - - - - - - - 56 Table.4.4 DO with SSB mixer summary - - - - - - - - - - - - - - - - - - - - - - - - - 57 Table.5.1 and PM relation - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 64 Table.5.2 Expect Specification - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 70 List of Figures Figure.2.1 Feedback system - - - - - - - - - - - - - - - - - - - - - - - - - - 3 Figure.2.2 Evolution of oscillatory system with time - - - - - - - - - - - - - - - - - - - 4 Figure.2.3 Views of oscillatory feedback system - - - - - - - - - - - - - - - - -5 Figure.2.4 (a)Ideal and (b)realistic LC tanks - - - - - - - - - - - - - - - - - - - - - - - - 6 Figure.2.5 Conversion between a series and a parallel combination - - - - - - -6 Figure.2.6 Conversion between a tank and three parallel components - - - - - - - - -8 Figure.2.7 (a)Magnitude (b)phase of the impedance of the tank as a function of frequency - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 8 Figure.2.8 Common Source stage in feedback - - - - - - - - - - - - - - - - - - - - - - - 9 Figure.2.9 Two Common Source stage in a cascade - - - - - - - - - - - - - - - - - - - -9 Figure.2.10 Loop gain characteristics of the circuit shown in Figure.2.9 - - - - - - 10 Figure.2.11 (a) Redrawing of the oscillator shown in Figure.2.9 (b) another redrawing of the circuit (c) additional tail current source to lower supply sensitivity - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10 Figure.2.12 A MOSFET C-V characteristic - - - - - - - - - - - - - - - - - - - - - - 11 Figure.2.13 (a)MOS varactor structure (b)varactor in depletion mode (c)varactor in accumulation mode (d)C-V characteristic - - - - - - - - - - - - - - - - - - - - - - - - - - 12 Figure.2.14 Effects of channel resistance in MOS varactor - - - - - - - - - - - - - - -12 Figure.2.15 VCO topology - - - - - - - - - - - - - - - - - - - - - - - - - - 13 Figure.2.16 Three varactors with different gate-doping - - - - - - - - - - - - - - - - -13 Figure.2.17 Output spectrum of ideal and actual oscillators - - - - - - - - - - - - - - 14 Figure.2.18 A definition of quality factor - - - - - - - - - - - - - - - - - - - - - - - - - 14 Figure.2.19 (a) N-core VCO (b) P-core VCO - - - - - - - - - - - - - - - - - - - - - - - 15 Figure.2.20 NP-core VCO - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 16 Figure.2.21 (a) Injection of a signal into an oscillator (b) small- signal model - - -17 Figure.2.22 (a) Two oscillators coupled to each other (b) implementation of (a) - 18 Figure.2.23 small-signal model of coupled oscillators - - - - - - - - - - - - - - - - - -19 Figure.2.24 (a) In-phase (b) anti-phase - - - - - - - - - - - - - - - - - - - - - - - - - - 19 Figure.2.25 Vector diagrams for in-phase coupling - - - - - - - - - - - - - - - - - - - 20 Figure.2.26 In-phase coupling of several oscillators - - - - - - - - - - - - - - - - - - -20 Figure.2.27 (a) Vector diagrams for anti-phase coupling (b) effect of current addition (c) deviation from resonance frequency - - - - - - - - - - - - - - - - - - - - - -22 Figure.2.28 Oscillator tuning through variation of coupling factor - - - - - - - - - -23 Figure.3.1 (a) A symmetric inductor (b) a transformer architecture - - - - - - - - -26 Figure.3.2 (a) Model of an inductor (b) a transformer- - - - - - - - - - - - - - - - - - 27 Figure.3.3 Two-port transformer - - - - - - - - - - - - - - - - - - - - - - - - - - 28 Figure.3.4 Transformer (a) equivalent inductance (b) quality factor - - - - - - - - - 29 Figure.3.5 (a) Re(Zin) (b) Im(Zin) (c) Q of the transformer (d) Q simulated by HSPICE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 30 Figure.3.6 Transformer layout - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 31 Figure.3.7 VCO architecture - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 31 Figure.3.8 Die photo and the chip package on PCB - - - - - - - - - - - - - - - - - - - 33 Figure.3.9 Spectrum of the max and min frequency - - - - - - - - - - - - - - - - - - - 33 Figure.3.10 Frequency range - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 34 Figure.3.11 Phase noise at center frequency - - - - - - - - - - - - - - - - - - - - - - - -34 Figure.3.12 Relation between phase noise and VCO control voltage - - - - - - - - -34 Figure.4.1 (a) Four phases by ILFD (b) by two differential VCOs - - - - - - - - - - 37 Figure.4.2 Classical injection-locked oscillator topology - - - - - - - - - - - - - - - -38 Figure.4.3 Proposed Injection-locked QVCO - - - - - - - - - - - - - - - - - - - - - - - 39 Figure.4.4 Differential control tuning range - - - - - - - - - - - - - - - - - - - - - - - -40 Figure.4.5 Timing diagram of the switches - - - - - - - - - - - - - - - - - - - - - - - - 40 Figure.4.6 Waveform of injection-locked QVCO - - - - - - - - - - - - - - - - - - - - -41 Figure.4.7 Phase noise at 1MHz offset - - - - - - - - - - - - - - - - - - - - - - - - - - - 41 Figure.4.8 Die photo and chip with packaging on PCB - - - - - - - - - - - - - - - - -42 Figure.4.9 Spectrum at 10.16GHz - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 42 Figure.4.10 Measured phase noise - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -42 Figure.4.11 (a) Regulator and power supply models (b) the spectrum instrument without connecting to any signals (c) connected to power supply (d) connected to power supply through regulator model (e) measured without regulator (f) measured with regulator - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 43 Figure.4.12 (a) Distributed oscillator topology (b) frequency doubler - - - - - - - -45 Figure.4.13 Working states of the doubler - - - - - - - - - - - - - - - - - - - - - - - 46 Figure.4.14 SSB up-conversion circuit - - - - - - - - - - - - - - - - - - - - - - - - - - - 47 Figure.4.15 Block of Distributed-Oscillator - - - - - - - - - - - - - - - - - - - - - - - -47 Figure.4.16 (a) Transformer model (b)transformer layout. - - - - - - - - - - - - - - - 50 Figure.4.17 SSB mixer model with mismatches - - - - - - - - - - - - - - - - - - - - - 50 Figure.4.18 Output waveform - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -52 Figure.4.19 Frequency range - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -52 Figure.4.20 Output phase noise - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -52 Figure.4.21 Frequency doubler simulation - - - - - - - - - - - - - - - - - - - - - - - - -52 Figure.4.22 SSB mixer simulation - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -53 Figure.4.23 The microphotograph and PCB photo of the chip - - - - - - - - - - - - -53 Figure.4.24 (a) Center frequency tone (b) phase noise - - - - - - - - - - - - - - - - - 54 Figure.4.25 Frequency range - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -54 Figure.4.26 RF_Choke, Mini-circuit, and Anritsu bias circuit - - - - - - - - - - - - -56 Figure.4.27 DO with SSB mixer measurements: (a) Spectrum range and phase noise (b) tuning range (c) phase noise of all points - - - - - - - - - - - - -57 Figure.5.1 Synthesizer architecture - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 59 Figure.5.2 State diagram of PFD - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -59 Figure.5.3 PFD architecture and its timing diagram - - - - - - - - - - - - - - - - - - - 60 Figure.5.4 CP Architecture - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -61 Figure.5.5 (a) Unevenness of the Up and Dn pulse (b) mismatch of charge and discharge current source - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -62 Figure.5.6 Charge-Pump topology of the synthesizer - - - - - - - - - - - - - - - - - - 62 Figure.5.7 The second order low pass filter - - - - - - - - - - - - - - - - - - - - - - - - - - 62 Figure.5.8 Bode plot of the second order filter - - - - - - - - - - - - - - - - - - - - -64 Figure.5.9 Regenerative Miller divider architecture - - - - - - - - - - - - - - - - - - - 65 Figure.5.10 VCO and Miller divider - - - - - - - - - - - - - - - - - - - - - - - - - - - - 65 Figure.5.11 Phase-selection circuit - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 66 Figure.5.12 VCO and Miller divider waveform - - - - - - - - - - - - - - - - - - - - - -67 Figure.5.13 VCO tuning range and corner - - - - - - - - - - - - - - - - - - - - - - - - -67 Figure.5.14 Power supply variation within 10% - - - - - - - - - - - - - - - - - - - - - 68 Figure.5.15 Phase selection circuit simulation - - - - - - - - - - - - - - - - - - - - - - 68 Figure.5.16 Matlab simulink simulation architecture - - - - - - - - - - - - - - - - - - 69 Figure.5.17 Simulink VCO control voltage simulation - - - - - - - - - - - - - - - - - 69 Figure.5.18 Spectre_RF VCO control voltage - - - - - - - - - - - - - - - - - - - - - - -69 Figure.5.19 Synthesizer layout - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 70 Figure.5.20 Chip package model - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 71 Figure.5.21 Output open-drain model - - - - - - - - - - - - - - - - - - - - - - - - - - - -71zh_TW
dc.language.isoen_USzh_TW
dc.publisher電機工程學系所zh_TW
dc.relation.urihttp://www.airitilibrary.com/Publication/alDetailedMesh1?DocID=U0005-2008200714462400en_US
dc.subjectFrequency Synthesizeren_US
dc.subject頻率合成器zh_TW
dc.title具有高效能且高頻壓控振盪器的除小數頻率合成器之設計zh_TW
dc.titleDesign of a Fractional-N Frequency Synthesizer with High-performance and High-Frequency Voltage-Controlled Oscillatorsen_US
dc.typeThesis and Dissertationzh_TW
item.languageiso639-1en_US-
item.openairetypeThesis and Dissertation-
item.cerifentitytypePublications-
item.grantfulltextnone-
item.fulltextno fulltext-
item.openairecristypehttp://purl.org/coar/resource_type/c_18cf-
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