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標題: 低延遲的IEEE802.11i加解密處理單元設計與VLSI實作
VLSI Implementation of Low Latency IEEE 802.11i Cryptography Processing Unit
作者: 李俊典
Li, Jun-Dian
關鍵字: IEEE 802.11i;對稱式加密法;AES;RC4;Low latency;WEP;TKIP;CCMP;硬體架構
出版社: 電機工程學系所
IEEE 802.11i為無線區域網路的安全標準規格,並定義了三種與資料保密性有關的演算法,即WEP、TKIP與CCMP。WEP與TKIP的加解密核心為RC4演算法,而CCMP的加解密核心採用AES演算法。RC4演算法與AES演算法都屬於對稱式加密法的一種,此加密法的特性是傳送端與接收端須共享一把相同的祕密金鑰,才能達到資料的保密性。
在本論文的研究中,我們使用了Verilog硬體描述語言來實現IEEE 802.11i的加解密硬體架構,並依照cell-based流程來設計與驗証。由於RC4演算法的硬體實現需使用到一個記憶體,所以我們利用Artisan Standard Library SRAM Generator來產生。對於要加密的一個封包,不論封包長度為多少位元組,RC4有其一固定的延遲週期,此延遲會造成過低的資料吞吐量,尤其是當封包長度愈短時。因此在設計上,我們使用[8]中所提出的16-bit packed記憶體演算法來減少RC4的固定延遲週期,以提升加密時整體的資料吞吐量。在AES演算法方面,由於IEEE 802.11傳輸資料以1-byte為單位,因此使用原始128-bit的硬體架構來設計AES,將造成不必要的面積成本。取而代之,我們採用了32-bit的AES硬體架構來節省面積。
最後,在電路合成方面,我們透過Synopsys Design Compiler在TSMC 0.18um的製程下完成。合成後的面積在不包含記憶體的情況下,閘數量約為44,300,最高工作頻率約為51MHz,而在50MHz的頻率下所測得的功率消耗為12.61mW。

IEEE 802.11i is the security standard specification of wireless local area network, and it defines three algorithms which are related to the data confidentiality, that is, WEP, TKIP, and CCMP. The cipher core of the WEP and TKIP is the RC4 algorithm while the cipher core of the CCMP is the AES algorithm. Both of the RC4 and AES algorithms are one of the symmetric ciphers, whose feature is that the transmitter and the receiver must share one same secret key to achieve the data confidentiality.
In the research of this thesis, we use Verilog hardware description language to model and implement the cipher architecture of the IEEE 802.11i, then we use the cell-based design flow to verify our design. Since the hardware implementation of the RC4 algorithm needs to use a memory, we generate the memory with the Artisan Standard Library SRAM Generator. For a ciphered packet, regardless of the length of the packet data bytes, the RC4 has a constant latency which will generate the excessively low throughput when the packet length is too short especially. Therefore, in our implementation, we use the 16-bit packed memory algorithm proposed by [8] to reduce the constant latency in the RC4 algorithm, and the 16-bit packed memory algorithm can improve the overall throughput in the encryption. As for the AES algorithm, due to the byte-wise data transmission in the IEEE 802.11, the design will produce the unnecessary area cost if we implement the AES algorithm with the conventional 128-bit architecture. In place of the 128-bit architecture, we employ the 32-bit AES architecture to reduce the area cost.
Finally, we synthesize our architecture through the Synopsys Design Compiler in the TSMC 0.18um process. If we don't take the memory into account, the residual area after the synthesis is about 44,300 gate counts, and the maximum frequency is approximately 51MHz, and then the power consumption at 50MHz frequency is 12.61mW.
Appears in Collections:電機工程學系所

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