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標題: 改良區塊型低密度同位元檢查碼解碼器設計與架構
Architecture design of the Modified Block-Type Low-Density Parity-Check Codes Decoder
作者: 吳聲東
Wu, Sheng-Dong
關鍵字: Low-Density Parity-Check (LDPC);低密度同位元檢查碼;decoder;encoder;hardware architecture;解碼器;編碼器;硬體架構
出版社: 電機工程學系所
引用: [1] R. G. Gallager, “Low density parity check codes,” IRE Trans. Inform. Theory, vol. IT-8, pp. 21-28, Jan. 1962. [2] D. J. C. MacKay, “Near Shannon limit performance of low density parity check codes,” Electronics Letters, vol. 33, pp. 457-458, Mar. 1997. [3] T. J. Richardson and R. L. Urbanke, “Efficient encoding of low-density parity-check codes,” IEEE Trans. Inform. Theory, vol. 47, pp. 638-656, Feb. 2001. [4] F. R. Kschischang and B. J. Frey, and H. -A. Loeliger, “Factor graphs and the sum-product algorithm,” IEEE Trans. on Inform. Theory, vol. 47, pp. 498-519, Feb. 2001. [5] S. Myung, K. Yang, and J. Kim, “Quasi-cyclic LDPC codes for fast encoding,” IEEE Trans. Inform. Theory, vol. 51, pp. 2894-2901, Aug. 2005. [6] E. Eleftheriou and S. Olcer, “Low-density parity-check codes for multilevel modulation,” in Proc. IEEE Int. Symp. Information Theory (ISIT2002), pp. 442, July 2002. [7] H. Zhong and T. Zhang, “Block-LDPC: a practical LDPC coding system design approach,” IEEE Trans. Circuits and Systems-part I, vol. 52, pp. 766-775, April 2005. [8] S.-M. Kim and K. K. Parhi, “Overlapped decoding for a class of quasi-cyclic LDPC codes,” IEEE Workshop Signal Processing Systems, pp. 113-117, 2004. [9] Z. Cui and Z. Wang, “Area-efficient parallel decoder architecture for high rate QC-LDPC codes,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS’06), pp. 5107-5110, May 2006. [10] S. L. Howard, V. C. Gaudet, C. Schlegel, and C. Schlegel, “Soft-bit decoding of regular low-density parity-check codes,” IEEE Trans. Circuits and Systems-part II, vol. 52, pp. 646-650, Oct. 2005. [11] M.-Y. Park, W.-C. Lee, J.-H. Kwak, C.-H. Cho, and H.-M. Park, “A demapping method using the pilots in COFDM system,” IEEE Trans. Consumer Electronics, vol. 44, pp. 1150-1153, Aug. 1998. [12] 施信毓, “VLSI Designs of LDPC Codec for IEEE 802.16e System,” 國立台灣大學碩士論文,中華民國九十五年六月。 [13] 林凱立, “High-Throughput Low-Density Parity-Check Code Decoder Designs,” 國立交通大學碩士論文,中華民國九十四年七月。
本論文提出一種結合低密度同位元檢查碼解碼設計方法,我們稱作改良式的區塊型同位元檢查碼(Modified Block-Type LDPC),做一個系統架構的實現。B-LDPC是一種QC-LDPC的特殊情形,由於結構上的簡化,他可以做有效的編碼。我們建立一個非正規的同位元檢查碼的排列方法,來得到一種節省面積的設計,以及好的錯誤更正能力,以及可實現的硬體架構。Modified B-LDPC解碼利用了min-sum algorithm(MSA)和利用位元節點單元(BNU)及檢查節點單元(CNU)來作運算。不同的區塊矩陣的大小情況之下,Modified B-LDPC可以提供較高的throughput但部會造成太多的效能的降低。

The target of the next generation wireless communication system is to transmit higher data rate and have a larger coverage area. However, radio transmission power needs to be kept to a minimum due to regulation and system power consumption. Thus, we can not achieve the target problem by increasing transmission power. Forward-error- correction (FEC) system can be employed to reach this target. The advanced FEC is the key technique in the next generation wireless communication system.
There are many up-to-date standards that take LDPC into consideration. For example, the next generation satellite communication DVB-S2 standard uses 64800-bit LDPC codes. By improving FEC, the data transmission throughput can get 30% up. The coderates of wireless network 802.11n standard are 1/2 to 5/6 that can support different levels of data protection.
In the thesis, a combined Low-Density Parity-Check (LDPC) code decoding design method, called modified Block-Type LDPC (B-LDPC), for realistic LDPC coding system architectures is presented. The B-LDPC code, which is a special class of quasi-cyclic LDPC (QC-LDPC), has an efficient encoding algorithm owing to the simple structure of their parity-check matrices. A proposed distribution of irregular parity-check matrix for the modified B-LDPC is developed so that we can obtain an area-efficient decoder design, good error correction performance, and achievable architecture implementation. The modified B-LDPC code decoding utilizes the iterative min-sum algorithm (MSA) and its decoding architecture design employs the operations of bit node unit (BNU) and check node unit (CNU). Different block matrix sizes for parity-check matrix can be adopted so that the modified B-LDPC code decoding improves the throughput without obvious performance degradation.
其他識別: U0005-2108200711363400
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